Load/Strain (Module G5)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 165 of 330BUSYIndicates the module is currently performing either BIT/OPEN detection or a background Calibration. Resistancedata is not being updated while BUSY is active (BUSY = ‘1’).REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0BUSY X X X X X X X X X X X X X X X DBIT/OPEN IntervalTime interval between successive BIT/OPEN detection tests. LSB = 60ms (A/D update rate). Minimum of 1.2s (20LSB’s) is required. Writing ‘0’ to this register disables BIT/OPEN detection. Default is 20s.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0BIT/OPEN INTERVAL D D D D D D D D D D D D D D D DCAL IntervalTime interval between successive background calibrations. LSB = 60ms (A/D update rate). Minimum of 1.2s (20LSB’s) is required. Writing “0000” to this register disables background calibration. Writing a “FFFF” forces animmediate background calibration, with the register automatically being set back to “0000” upon completion of thebackground calibration. Default is 10 min.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0CAL INTERVAL D D D D D D D D D D D D D D D DBIT StatusCheck the corresponding bit for a channel’s BIT Status. A “0” =Normal; “1” = Non-functional A/D conversion.Reading any status bit will unlatch the entire register. Detected after time interval specified by BIT/OPEN Intervalregister. BIT Status is part of background testing and the status register may be checked or polled at any giventime.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0BIT Status X X X X X X X X X X Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1Open Detection StatusCheck the corresponding bit of the Open Detection Status register for open/disconnected RTD or leads for eachchannel. A “0” =Normal, “1” = Open. Detected after time interval specified by BIT/OPEN Interval register.Reading any status bit will cause that bit to be unlatched. Open Detection Status is part of background testing andthe status register may be checked or polled at any given time.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Open Detection Status X X X X X X X X X X Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1BIT Status Interrupt EnableSet the bit to enable interrupts for the corresponding channel. When enabled, a non-compliant channel will triggeran interrupt. Default is 00h to disable all channels.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0BIT Status Interrupt Enable X X X X X X X X X X Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1
