I/O Digital TTL/CMOS (Module D7)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 116 of 330MUXProtectiveCircuits1Wrap-AroundTestChannelTTL Buffer 1StateMachineTTL Module Block Diagram16116OUT 1IN 1TTL Buffer 16OUT 16IN 16IN/OUT 1IN/OUT 16Module BusUser InterfaceI/O DIGITAL TTL/CMOS (MODULE D7)Principle of OperationThis module provides (up to) 16 individualDigital TTL/CMOS I/O channels (depending onplatform and I/O connector pin availability),which are programmable for either Input orOutput, and include extensive diagnostics.Interrupt(s) can be selected, for each channel,to indicate transition on rising edge, transitionon falling edge, or both. De-bounce circuits foreach channel offer a selectable time delay toeliminate false signals resulting from contactbounce commonly experienced withmechanical relays and switches. EachTTL/CMOS channel has an internal 100KΩpull-down resistor. All inputs are continuallyscanned and the data is double buffered forimmediate availability.Automatic Background Built-InTest (BIT)/Diagnostic CapabilityThe module contains automatic background BIT testing that verifies channel processing (data read or write logic), tests forover-current conditions and provides status for threshold signal transitioning. Any failure triggers an Interrupt (if enabled) withthe results available in status registers. The testing is totally transparent to the user, requires no external programming andhas no effect on the operation of this card. It can be enabled or disabled via the bus (see further details in register description),and continually checks that each channel is functional. This capability is accomplished by an additional test comparator that isincorporated into each 16-channel module. The test comparator is sequentially connected across each channel and iscompared against the operational channel. Depending upon the configuration, the Input data read or Output logic written of theoperational channel and test comparator must agree or a fault is indicated with the results available in the associated statusregister. Low-to-High and High-to-Low logic transitions are indicated. Additional testing of output logic indicates Over-currentcondition when output logic is invalid for a period greater than 80μs.Write OutputWhen a channel is configured for Output, write logic level High (“1”) or Low (“0”) to associated channel bit, in 16-bit binaryword. Each bit corresponds to one of 16 channels.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ChannelWRITE OUTPUT D D D D D D D D D D D D D D D D D=DATA BIT
