Revision Page68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 327 of 330REVISION PAGERevision Description of Change Engineer Date2014-12-19-0947Added note to S-D Descriptions for Bandwidth. Select register AS 12/19/142014-08-28-1736ECO# C02636: 1. 75PPC1 SC1 pinout clarification; 2. 79C3 - addedfront panel I/O trigger reference designations/details 3. K9 description- pull-up/down "bank" designation correction.; 4. SIU33 HW manual -clarified power dissipation to 75W (max.) (pg. 6, specs/electrical) 5. AllGEN2 and higher platforms - added high-word register(s) foraccomodating 32-bit serial numbersAS 08/28/142014-03-07-1718VARIOUS: Document maintenance: 1. 75PPC1 I/O pinouts - frontpanel I/O pinout MOD2 corrected; From: J3 To: J4. 2. J5, J8 modulespec output range clarified (J5 is +/-20V, J8 is +/-80V max ranges)(retro-clarification). 3. KA module spec/BIT availability/operationclarified.; 4. 73SD3 Spec/Manual updated to include BIT logiccompatability function register. 5. L(R)VDT simulation modules (2-CH& 3-CH) - clarified phase offset control (removed previous "pending").6. Encoder (E7) module clarifications: A) Added "Counter LatchRegister" function. B) Clarified "Latch on I" function. C) Clarified"Counter Status Register". 7. L(R)VDT (2-CH&3-CH) modulesclarified: updated "Set Offset Phase" function (documented/removed"pending" status). 8. 75SD1 manual/specification update: removedreference of "Save" feature (retro-clarification). 9. Added G3thermocouple measurerment module to spec, description and registermaps - all "GEN3" platforms that support the function. 10. 75C5 -clarified P/N digit for bus master.AS 03/07/142014-01-22-1201ECO# C02392; Standard documentation maintenance: 1. Addedsense line to 75DS2/64CS4 DLV 2-CH module pinouts (whereapplicable) 2. SIU6 Datasheet - clarified MIL-STD-461F test inclusioncompliance 3. 76CS3 optional AC REF P/N clarification (W3 is 28-115Vrms). 4. CANBus (P6 and PA) memory map inclusion of interruptvector registers 5. 79C3 (GEN3) inclusion of PC module. 6. SIU6pinout correction: Pg. 21 J2-45 From: A-P2-E10 To: A-P0-E10; J2-66From: A-P2-E13 To: A-P0-E13; Pg. 22 J3-57 From: A-P0-Z21 To: A-P2-Z21 7. General P8/PC module descriptions: clarified half duplexand extended mode RTS/CTS for front panel I/O (if platformsupported) operation(s).; 75DS2 MB spec clarified (no +/-12V requiredfor base MB (modules only). 8. Clarified applicable MFIO P/Ndesignators for W1, W2, W3 frequency range (note to see spec forapplicable Vout ranges).AS 01/22/142013-07-01-13331) D8 (Diff I/O) module spec/memory map clarification - 11 CH w/ 16CH available on supported platforms. 2) Interrupts w/use of latchingregisters operation/clarification - all modules w/ supporting functions.3) NIU1 (data sheet/manual) clarification of mating connectors 4) H2Ethernet Switch module control register/function additions. 5) K6 PWMfunction added - Gen3 platforms only. 6) E7 Description (clarifications)to the Multiple Channel Read function. Removed the FPGA resistermap from the Interrupt Mapping. Changed and clarified the Interruptstatus bits.; 7) DLV (2CH) code table correction. 8) Arinc A4 registernaming sync with map. 9) D/S description - remove inferance of 2scomplement convention for angle data. 10) 75C5 and 75D4 platforms -initial Agile release (generic volume) Ops Manual/Specifications andAS 07/01/13
