Differential Multi-Mode Transceivers (Module D8)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 125 of 330Interrupt and Status Register Operation/ClarificationUnless otherwise specifically stated, the following represents a general operation/clarification note for the Interrupt operationand its associated/coinciding “latching” – type Status Register(s): An interrupt will be generated when the specific channel interrupt is enabled and there is a detection of the respectivechannel transition change in the appropriate channel of the corresponding Status Register. Status Register(s) are “latching”; as defined, any noted transitional change on any channel will “latch” the entireStatus Register. Once latched, there will be no further state change “sensed” by the interrupt mechanism, hence, no further interrupts. The act of reading a Status Register will “unlatch” that particular status register (doesn’t necessarily clearimmediately, but will update and clear on the next internal loop cycle). Because transitional changes will “latch” the Status Register, and the interrupt mechanism uses the Status Registeras its trigger, before an interrupt is generated and after an interrupt is generated, the Status Register must be read“until cleared”.The following is recommended for Interrupt and associated Status Register initialization and handling (assuming vectors andinterrupt level (if appropriate) are being properly/appropriately initialized): Power-up- Perform normal initializations (card/channel initializations/interrupt vector/interrupt enable/ etc.).- Perform a software read loop (part of the host application software initialization routine(s)) on the specificStatus Registers of concern (“loop to clear”) - this would also be similar to an Interrupt Service Routine (ISR)“loop to clear” function.Ex: Running the ‘loop to clear’ on the appropriate Status Register(s) during the initialization (after I/Ofunction is programmed) will ensure any spurious transitions detected on power-up are “cleared” and thechannel(s) are primed and ready to trigger for interrupts.- - for the specific interrupt enabled channels- Initial interrupt should occur (if initialized/enabled) Interrupt Software Routine (ISR)The ISR is typically a software (SW) handling branch (part of host application software) structured to “loop to readand clear” the specific Status Register(s) associated with the interrupt type (i.e. H-L or L-H transition). The SW loopshould “read” the Status Register until cleared (typically, this is 2 or 3 times) to ensure any other channel transitionsare accounted for during the ISR process while the respective Status Register(s) were “latched” – the act of readingthe Status Register(s) allows the channel(s) that set the transition/latch to clear and effectively “re-arm” for the nexttransition to occur.Ex: The ISR should have the ‘loop to clear’ – to ensure all transitions are accounted for – and the channel(s) areready to trigger for next event.NOTES: Any channel on the Status Register could latch the register regardless if the channel(s) interrupts are enabled or not. For Status Registers that are bit mapped for either input or output, programming outputs that change transitions willalso “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should beperformed to ensure the Status Register is unlatched, clear and ready to trigger on next event.
