D/S Three Channel (Module 6*)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 243 of 330D/S Status, Phase Lock LossCheck the corresponding bit of the D/S Phase Lock Loss Register for status of the phase lock between thereference input and signal output for each active channel. A ”1” means Phase Lock Loss has occurred, “0”means Phase Lock OK on active channels. Channels that are inactive are also set to “0”. (Phase Lock loss isdetected after 2 seconds). Phase Lock monitoring is always enabled. Any D/S Phase Lock Loss status failure,transient or intermittent, will latch the D/S Phase Lock Loss Status Register. Reading will unlatch register.D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D/S Status, Phase Lock Loss X X X X X X X X X X X X X CH3 CH2 CH1D/S Set Phase OffsetThe phase of each individual channel may be offset from Reference. The phase may be adjusted at a resolutionof 0.1 deg / bit. Program the desired lead or lag in integer as a 2’s complement word format. For example, ifchannel 1 output signal is to lead the reference signal by 1.6 degrees, program the corresponding channel phaseregister to 16 (10h). If channel 1 output signal is to lag the reference signal by 1.6 degrees, program thecorresponding channel phase register to -16 (FFF0h). Phase shift range is -90 <= x <= 90.D/S Status, BIT TestCheck the corresponding bit of the D/S BIT Test Status Register for status of BIT (Test-Accuracy) Testing foreach “active” channel. A ”1” means Accuracy Failed; “0” means Accuracy OK. Channels that are “inactive” arealso set to “0”. The status bits will be set to indicate an accuracy (0.2º) problem and the results can be read fromD/S Status Registers within 2 seconds and, if enabled, an interrupt will be generated (See Interrupt Register).This test continuously sequences between the channels on the card with each output being measured forapproximately 180mSec. If the measured angle has an error greater the 0.2º, a flag will be set in the appropriateregister. If the input angle is stepped more then 0.2º during a test cycle, the test cycle will not generally indicatean error.D/S channels, by default, are set for monitoring the channel background BIT (Built-In-Test) status reporting; “ON”or “ACTIVE”. The front panel BIT LED illuminates (Red) if any channel reports a BIT fault. For BIT status to workproperly on an “active” channel, the D/S channel must have a valid Reference source applied and the D/Schannel power set to “ON” (so there is a valid signal being generated). If channels are not being used, it isrecommended that the channel BIT status report be turned off (or set INACTIVE). However, it should be notedthat the channel BIT status register latches the contents of a failure until read. Simply setting the channel“INACTIVE” will not clear the BIT status register or extinguish the front panel BIT fault LED if a fault waspreviously detected.The D/S BIT Test Status register should be queried (read) to insure the register is unlatched which will enable theBIT status register to be re-written during next status update (which, when the channel is set INACTIVE, shouldclear the fault). Once this is done, the front panel BIT LED will extinguish – as long as the channels that are activeare working properly and the channels not being utilized are set INACTIVE.Note: When D/S Wrap Select External/Internal register is set for “external”, the BIT wrap will be read from theexternal amplifier wrap input signals (See pin-out). Also, the BIT tolerance will be adjusted for the amplifieraccuracy specification.D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D/S Status, BIT Test X X X X X X X X X X X X X CH3 CH2 CH1
