North Atlantic 68C3 Operation Manual
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Contents
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68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 9 of 330Data Read ........................................................................................................................................................................... 107Range & Polarity.................................................................................................................................................................. 107Filter Break Frequency ........................................................................................................................................................ 107Latch All A/Ds ...................................................................................................................................................................... 107D0 Test Range .................................................................................................................................................................... 107D0 Test Voltage ................................................................................................................................................................... 108Calibration Interval Delay .................................................................................................................................................... 108FIFO Buffer Operational Description ................................................................................................................................... 108FIFO Buffer Data (per channel): ..................................................................................................................................... 108Words in FIFO (per channel): ......................................................................................................................................... 108Hi-Threshold (per channel): ............................................................................................................................................ 108Low-Threshold (per channel): ......................................................................................................................................... 108Delay (per channel): ....................................................................................................................................................... 108FIFO Size (per channel): ................................................................................................................................................ 109Sample Rate (per channel): ............................................................................................................................................ 109Clear FIFO (per channel): ............................................................................................................................................... 109Buffer Control (per channel):........................................................................................................................................... 109Trigger Control (per channel): ......................................................................................................................................... 110FIFO Status (per channel): ............................................................................................................................................. 110Interrupt Enable (per channel): ....................................................................................................................................... 110Software Trigger (per channel): ...................................................................................................................................... 111Clock Rate Input .................................................................................................................................................................. 111Test Enable ......................................................................................................................................................................... 112Test (D2) Verify ................................................................................................................................................................... 112Active Channels................................................................................................................................................................... 112BIT Status ............................................................................................................................................................................ 112Open Status ........................................................................................................................................................................ 113BIT Status Interrupt Enable ................................................................................................................................................. 113Open Status Interrupt Enable .............................................................................................................................................. 113BIT Interrupt Vector ............................................................................................................................................................. 113Open Interrupt Vector .......................................................................................................................................................... 113FIFO Buffer Interrupt Vector ................................................................................................................................................ 113Interrupt and Status Register Operation/Clarification .......................................................................................................... 114A/D (MODULES C1, C2, C3 & C4) PCI MEMORY MAP...................................................................................... 115I/O DIGITAL TTL/CMOS (MODULE D7) .............................................................................................................. 116Principle of Operation .......................................................................................................................................................... 116Automatic Background Built-In Test (BIT)/Diagnostic Capability ......................................................................................... 116Write Output ........................................................................................................................................................................ 116Read Input or Output ........................................................................................................................................................... 117External VCC Select ............................................................................................................................................................ 117De-bounce Time .................................................................................................................................................................. 117De-bounce LSB ................................................................................................................................................................... 117Input/Output Format ............................................................................................................................................................ 117Reset Over-Current ............................................................................................................................................................. 118Status Indications ................................................................................................................................................................ 118Interrupt Vectors .................................................................................................................................................................. 118Interrupt and Status Register Operation/Clarification .......................................................................................................... 119I/O DIGITAL TTL/CMOS (MODULE D7) PCI MEMORY MAP ............................................................................. 120DIFFERENTIAL MULTI-MODE TRANSCEIVERS (MODULE D8) ...................................................................... 121Principle of Operation .......................................................................................................................................................... 121Automatic Background Built-In Test (BIT) / Diagnostic capability ........................................................................................ 121 |
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