I/O Relay (Module KN, KL)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 195 of 330I/O RELAY (MODULE KN, KL)Principle of OperationThis module provides four individual single pole user DPDTForm C (changeover / break-before-make type) relay I/Ochannels. The 2nd set of pole contacts is used for Built-In-Test(BIT). Each channel has a common input terminal (C), anormally closed output terminal (N/C) and a normally open(N/O) output terminal. The channel is commanded to energizeor de-energize the relays (close or open) so that the signalprovided on (C) may be switched/directed to either the (N/C) or(N/O) terminals. Interrupts can be enabled/configured for eachchannel to indicate if a BIT fault (state of secondary set ofcontacts does not match command) occurs. Internal de-bouncecircuits for each channel provide the required time delay toeliminate false signals resulting from contact bounce commonlyexperienced with mechanical relays and switches. The KNimplements “non-latching” type relays. The relays utilized onthe KN module power-on default remain de-energized or in the“reset position” until commanded to the “set” position. Thecontacts will then remain in the “set” position until commandedto the “reset” position or if power is removed from the card/module. The KL implements “latching” type relays.The relays on the KL module utilize magnetic latching to assure that once a relay channel is ‘set’ or ‘reset’ (evenif power is removed from the card/module), the channel will remain at the last commanded position. Thesecondary set of contacts on each relay channel is utilized for BIT purposes and is continually scanned incomparison to commanded “set” (closed) or “reset” (open) conditions. Data is double-buffered for immediateavailability.Automatic Background Built-In Test (BIT) Diagnostic CapabilityThe module contains automatic background BIT testing that verifies channel processing from a secondary set ofcontacts (data read compared to write logic), and tests for relay state. Any discrepancy (or fault) triggers anInterrupt (if enabled) with the results available in status registers. The testing is totally transparent to the user,requires no external programming and has no effect on the operation of this card.Write OutputWrite a logic level High (“1”) (set/closed) or Low (“0”) (reset/open) to associated channel bit, in 16-bit binary word,to toggle/command between the “set” or “reset” of the channel respectively.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTIONx x x x x x x x x x x x 4 3 2 1 ChannelWRITE OUTPUT 0 0 0 0 0 0 0 0 0 0 0 0 D D D D D=DATA BITRead StateRead logic state High (“0”) or Low (“1”) as defined by relay state “OPEN” (reset) or “CLOSED” (set) respectively.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ChannelREAD I/O 0 0 0 0 0 0 0 0 0 0 0 0 D D D D D=DATA BITBuilt-In-Test(BIT)CH1-CToMotherboardFPGA/DSPFront and/or RearI/O connectionsCH1-N/CCH1-N/OCH2-CCH2-N/CCH2-N/OCH3-CCH3-N/CCH3-N/OCH4-CCH4-N/CCH4-N/OK(x) Multi-Channel Relay Module(“Reset” positions shown)
