ARINC 429/575 Six Channel, Tx/Rx (Module A4)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 59 of 330Channel Control HighType: binary wordRange: not applicableRead/Write: R/WInitialized Value: 0This register is used to clear the FIFOs and match memory. The channel reset bit will clear out Channel ControlLow and Interrupt Enable registers as well as reset the transmit and receive circuits. However, it will not reset thechannel Transmit FIFO Rate, Tx Buffer Almost Empty, and Rx Buffer Almost Full registers. If Schedule Interruptsare enabled in the Interrupt Enable register, then reading the Interrupt Status register will clear the bit in both theChannel Status and Interrupt Status registers. The Schedule Interrupt Clear bit D5 can be used to clear theSchedule Interrupt bit D10 in the Channel Status register if the interrupt is not enabled.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION1CONTROL HI X X X X X X X X X X X 0 0 0 0 1 TRANSMIT FIFO CLEARX X X X X X X X X X X 0 0 0 1 0 RECEIVE FIFO CLEARX X X X X X X X X X X 0 0 1 0 0 MATCH MEMORY CLEARX X X X X X X X X X X 0 1 0 0 0 CHANNEL RESETX X X X X X X X X X X 1 0 0 0 0 RESERVEDX X X X X X X X X X 1 0 0 0 0 0 SCHEDULE INTR. CLEARNote: 1. Firmware will clear bit. Allow 100us for command to complete.
