ARINC 429/575 Six Channel, Tx/Rx (Module A4)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 62 of 330Interrupt StatusType: binary wordRange: not applicableRead/Write: R/WInitialized Value: not applicableThis register describes the status of 12 different events. These events are latched when they occur and areenabled by their corresponding Interrupt Enable bits in the Interrupt Enable register. See specific registers forfunction description and programming. Reading this register clears the interrupts that were set. The Rx DataAvailable interrupt sets when the first data word is received into an empty receive FIFO. The Rx FIFO Overflow bitwill set whenever the receiver has to discard data because the receive FIFO was full and new data was received.The Schedule interrupt will set when the schedule interrupt command is executed in the programmed schedule.The Tx Complete interrupt will set when Tx Run goes inactive.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTIONINTERRUPT STATUS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RX DATA AVAILABLE0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 RX FIFO ALMOST FULL0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 RX FIFO FULL0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 RX FIFO OVERFLOW0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 TX FIFO EMPTY0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 TX FIFO ALMOST EMPTY0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 RESERVED0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 PARITY ERROR0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 RECEIVE ERROR0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 BUILT-IN-TEST ERROR0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 SCHEDULE INTERRUPT0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ASYNC DATA SENT0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 TX COMPLETE0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVEDTransmit FIFO Rate (Hi+Lo)Type: 20-bit unsigned integerRange: 0-FFFFFh , Rate High & Low Registers combinedRead/Write: R/WInitialized Value: 4Mode: FIFOBoth the Rate High Register and Rate Low Register combined together determine the Gap time betweentransmitted ARINC messages in FIFO transmit modes. Each LSB is 1 bit time. Rates less than 4 are not valid.This register does NOT get reset by a channel reset.RATE HIGH REGISTER RATE LOW REGISTERD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0X X X X X X X X X X X X D D D D D D D D D D D D D D D D D D D D
