3 CH DLV (5*) (PCI) MODULE MEMORY MAP68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 258 of 3303 CH DLV (5*) (PCI) MODULE MEMORY MAPModule Length = 800h000 Wrap LVDT Position Lo CH1 R 140 DLV Set Excitation Volt Lo CH1 W/R 300 DLV Write Position Lo CH1 W/R004 Wrap LVDT Position Hi CH1 R 144 DLV Set Excitation Volt Hi CH1 W/R 304 DLV Write Position Hi CH1 W/R008 Wrap LVDT Position Lo CH2 R 148 DLV Set Excitation Volt Lo CH2 W/R 308 DLV Write Position Lo CH2 W/R00C Wrap LVDT Position Hi CH2 R 14C DLV Set Excitation Volt Hi CH2 W/R 30C DLV Write Position Hi CH2 W/R010 Wrap LVDT Position Lo CH3 R 150 DLV Set Excitation Volt Lo CH3 W/R 310 DLV Write Position Lo CH3 W/R014 Wrap LVDT Position Hi CH3 R 154 DLV Set Excitation Volt Hi CH3 W/R 314 DLV Write Position Hi CH3 W/R330 OSC Set Voltage Lo W/R064 Wrap Excitation Voltage CH1 R 160 DLV Set Signal Volt Lo CH1 W/R 334 OSC Set Voltage HI W/R068 Wrap Excitation Voltage CH2 R 164 DLV Set Signal Volt Hi CH1 W/R 338 OSC Set Frequency Lo W/R06C Wrap Excitation Voltage CH3 R 168 DLV Set Signal Volt Lo CH2 W/R 33C OSC Set Frequency Hi W/R16C DLV Set Signal Volt Hi CH2 W/R070 Wrap Signal Voltage CH1 R 170 DLV Set Signal Volt Lo CH3 W/R 700 DLV Status, BIT Test R074 Wrap Signal Voltage CH2 R 174 DLV Set Signal Volt Hi CH3 W/R 704 DLV Reference Loss Interrupt Enable W/R078 Wrap Signal Voltage CH3 R 708 DLV Signal Loss Interrupt Enable W/R180 DLV Test Enable W/R 70C DLV BIT FAIL Interrupt Enable W/R080 Wrap Signal Loss Threshold CH1 W/R 188 D2 Test Verify W/R 710 DLV Phase Lock Loss Interrupt Enable W/R084 Wrap Signal Loss Threshold CH2 W/R 18C DLV Output Mode W/R088 Wrap Signal Loss Threshold CH3 W/R 198 DLV 2-W/4-W Select W/R 7C0 Vector Interrupt BIT Fail W/R7C4 Vector Interrupt REF Loss W/R08C Wrap Excitation Loss Threshold CH1 W/R 1C0 DLV Module Power Enable W/R 7C8 Vector Interrupt Signal Loss W/R090 Wrap Excitation Loss Threshold CH2 W/R 1C8 DLV Active Channel Select W/R 7CC Vector Interrupt Phase Lock Loss W/R094 Wrap Excitation Loss Threshold CH3 W/R1CC DLV Excitation Status R 768 Module Design Version R098 Channel 1 Frequency R 1D0 DLV Phase Lock Status CH1/2 R 76C Module Design Revision R09C Channel 2 Frequency R 1E8 DLV Set Phase Offset CH1 W/R 770 Module DSP Revision R0A0 Channel 3 Frequency R 1EC DLV Set Phase Offset CH2 W/R 774 Module FPGA Revision R0B0 Status, Signal Loss R 1F0 DLV Set Phase Offset CH3 W/R 778 Module ID Revision R
