Load/Strain (Module G5)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 164 of 330Filter ConfigurationThe A/D offers a lot of flexibility in the digital filter. The device has four filter options. The device can be operated with a sinc3or sinc4 filter, chop can be enabled or disabled, and zero latency can be enabled. The filter Configuration along with the PGAgain setting selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection.The following sections describe each filter type, indicating the available output data rates for each filter option. The filterresponse along with the settling time and 50 Hz/60 Hz rejection is also discussed.Filter Configuration D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTIONSINC3000SINGLEREJ60FS[9]FS[8]FS[7]FS[6]FS[5]FS[4]FS[3]FS[2]FS[1]FS[0]Data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 D=DATA BITSINC3Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set, the sinc3 filter is used.The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time. For a given output data rate, fADC, the sinc3filter has a settling time of 3/fADC while the sinc4 filter has a settling time of 4/fADC when chop is disabled. The sinc4 filter,due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar RMS noise andsimilar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4 filter givesbetter performance than the sinc3 filter for RMS noise and no missing codes.SINGLESingle cycle conversion enable bit. When this bit is set, the A/D settles in one conversion cycle so that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode isselected.REJ60This bit enables a notch at 60 Hz when the first notch of the SINC filter is at 50 Hz. When REJ60 is set, a filter notch is placedat 60 Hz when the SINC filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection.FS[9:0]FS[9:0] determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. Inassociation with the gain selection, they also determine the output noise (and, therefore, the effective resolution) of the device(Please refer to Table 6 through Table 17 of the A/D specification).When chop is disabled and continuous conversion mode is selected;Output Data Rate = (MCLK/1024)/FSWhere FS is the decimal equivalent of the code FS[9:0] and is in the range 1 to 1023, and MCLK is the master clockfrequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz.With chop disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chopis enabled;Output Data Rate = (MCLK/1024)/(N × FS)Where FS is the decimal equivalent of the code in FS[9:0] and is in the range 1 to 1023, and MCLK is the master clockfrequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is theorder of the SINC filter. The SINC filter’s first notch frequency is equal to N × output data rate. The chopping introducesnotches at odd integer multiples of (output data rate/2).
