Panasonic MN103S User Manual

Also see for MICROCOMPUTER MN103S: Application note Connection diagrams

Contents

Chapter 5Interrupt ControllerInterrupt Controller Operation V - 355.3 Interrupt Controller Operation5.3.1 Interrupt Types■ Reset InterruptsReset interrupts are interrupts with the highest priority level, and are generated by setting the NRST pin to “L” orwriting the CHIPRST flag of the reset control register from “0” to “1”. Registers are initialized by the reset inter-rupt, and a program is executed from 0’x40000000 address. Refer to [2.7.2 Reset Mode] for further details.■ Non-maskable InterruptsNon-maskable interrupts accept interrupts regardless of the values of the PSW interrupt enable flag (IE) and inter-rupt mask level IM2 to IM0. When the non-maskable interrupt is accepted, it branches to the interrupt processingprogram located at the addressees from 0x40000009~0x4003FFFF. After accessing the NMICR register to ana-lyze the interrupt factor, perform the interrupt processing and cancel the interrupt factor, the interrupt processingprogram returns to the normal program by the RTI instruction.Non-maskable interrupts have watchdog timer overflow interrupts and system error interrupts.Watchdog timer overflow interrupt occur when the WDCNE flag in the watchdog timer control register(WDCTR) is “1” and the watchdog timer overflows. When the watchdog timer interrupt generates, the watchdogtimer overflow interrupt request flag (WDIF) of the non-maskable interrupt control register (NMICR) is set to“1”.System error interrupt occur when an unmounted instruction is executed or other fatal error occurs. When the sys-tem error interrupt generates, the system error interrupt request flag (SYSEF) of the NMICR register is set to “1”...Interrupt Condition Register(ISR:0x00008034) is available for development of OS anddebugging...■ Level InterruptsLevel interrupts are interrupts that can control the interrupt level through the interrupt enable flag (IE) of the PSWand interrupt mask level (IM2 to IM0). The Level interrupts are interrupts from the interrupt group controllersexternal to the CPU core (in other word, peripheral interrupts), and correspond the groups and factors indicated inblock diagrams (Figure 5.1.1 to 5.1.4). Each interrupt group controller includes an interrupt control register(GnICR); and, the interrupt priority level can be set per interrupt group. It is also possible to set the same inter-rupt priority level in the interrupt groups. If interrupts of the same priority level are generated simultaneously, theinterrupts are accepted in the order of priority set by hardware (the group with the smallest group number takesthe highest priority).When the level interrupt is accepted, the upper 16 bits branch to “x’4000” and the lower 16 bits branch to theaddress of the interrupt vector address register (IVARn) corresponding to the interrupt level by hardware. Afterthe interrupt processing program accesses the IAGR register to analyze the interrupt group and the GnICR registerto analyze the interrupt factor, perform the interrupt processing and cancel the interrupt factor, it returns to thenormal program by the RTI instruction.