Chapter 5Interrupt ControllerControl Registers V - 95.2.2 Processor Status Word■ Processor Status WordThe interrupt enable flag and interrupt mask level flag are used as interrupt-related flags in the processor statusword (PSW). These flags are read- and write-enabled flags. For information about the PSW, refer to [Chapter 2CPU].Table:5.2.2 Processor Status WordTable: 5.2.3 shows the relationship between interrupt mask levels and acceptable interrupt levels.Table:5.2.3 Relationship between Interrupt Mask Levels and Interrupt Levels that Can be Acceptedbp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Flag - - S1 S0 IE IM2 IM1 IM0 - - - - V C N ZAt reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Access R R R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/Wbp Flag Description Set condition15-12 - - Refer to[ Chapter 2 CPU ]11 IEInterrupt enable 0: disabled1:enabledThis flag allows all interrupts to be accepted except for reset interruptsand non-maskable interrupts. When an interrupt is accepted, IE flag iscleared to “0” (interrupt disabled). Set IE flag to “1” when acceptingmultiple interrupts within the interrupt processing program.10-8IM2IM1IM0Interrupt mask level Specifies the interrupt mask level. When IE flag is “1”, the CPU coreaccepts the interrupt with level higher than the mask level.7-0 - - Refer to [ Chapter 2 CPU ]Interrupt mask levelAcceptable interrupt levelIM2 IM1 IM00 0 0 Interrupt disabled (only non-maskable interruptsaccepted.)0 0 1 00 1 0 0 to 10 1 1 0 to 21 0 0 0 to 31 0 1 0 to 41 1 0 0 to 51 1 1 0 to 6
