Chapter 3Clock GeneratorOperation III - 9..When the CPU clock (MCLK) is 40 MHz or over, change an access to the internal ROM to 3cycle access (ROMMC[1:0]=10) by the internal ROM access control register (ROMCTR)before the PLLSEL flag of the PLL control register (PCNT) is switched "0" to "1".The operation that is set to 2 cycle access is not guranteed.....When the PLLON and CKSEL [1:0] flags of the PCNT register are changed, reset the PLLSEL flag to“0” before the change and set to “1” after waiting over 200 μs...Setup Procedure Description(1) Set the multiplication ratioPCNT (0x0000AFF2)bp5: PLLSEL=0bp3: PLLON=0bp1: CKSEL1=0bp0: CKSEL0=1(1) Set the PLL multiplication ratio to 6 by the CKSEL 1 andCKSEL0 of the PLL control register (PCNT).Note: Set the frequency ( oscillation frequceny ×multiplication ratio) to 40MHz≤PLLOUT≤60MHz(2) Wait PLL lock timeover 200 μs (2) Wait 200 μs by the execution of the loop program etc.(3) Select PLL outputPCNT (0x0000AFF2)bp5: PLLSEL=1bp3: PLLON=0bp1: CKSEL1=0bp0: CKSEL0=1(3) Set the PLLSEL of the PLL control register (PCNT) to “1”to select the PLL output to the internal clock.Note: Do not change the values of PLLON, CKSEL1and CKSEL0.(4) Set the frequency of MCLK and IOCLKCKCTR (0x00008280)bp5: IOCLK1=1bp3: IOCLK0=1bp1: MCK1=1bp0: MCK0=1(4) Set the cycle division of MCLK and IOCLK. This settingis not necessary when MCLK=PLLOUT and IOCLK=1/2PLLOUT.
