Chapter 2CPU BasicsProgramming Model II - 7■ Processor Status Word (16-bit x 1)This register indicates the CPU status, and stores flags for operation results and interrupt mask level, etc.Table:2.3.1 Processor Status Wordbp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Flag - - S1 S0 IE IM2 IM1 IM0 - - - - V C N ZAt reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Access R R R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/Wbp Flag Description Set condition15-14 - - -13-12 S1S0 Software bit These are the software control bits for the operating system(OS). These bits cannot be used by general user programs.11 IE Interrupt enable0: disabled1: enabledThis flag permits and accepts all interrupts except reset andnon-maskable interrupts. When the CPU accepts an interruptrequest, the IE will be cleared to 0. Therefore, IE flag must beset to “1”, if nested interrupts need to be accepted in the inter-rupt processing program.10-8IM2IM1IM0Interrupt mask levelThe three bits defines the mask level from level 0 (000) to level7 (111), with level 0 being the highest mask level. The CPUaccepts only those interrupt requests of a level higher than themask level indicated here. When an interrupt is accepted, theIM flag is set to the priority level of that interrupt. Until the pro-cessing of the accepted interrupt is completed, the CPU doesnot accept interrupts with the same interrupt level or lower.7-4 - - -3 V Overflow flag0: When an overflow does not occurs in a signed value in thecourse of executing an operation.1: When an overflow occurs in a signed value in thecourse of executing an operation.2 C Carry flag0: When a carry or a borrow from the most significant bit(MSB) did not occur as a result of computation.1: When a carry or a borrow from the most significant bit(MSB) occured as a result of computation.1 N Negative flag0: When the most significant bit (MSB) is "0" as a result ofcomputation.1: When the most significant bit (MSB) is “1” as a result ofcomputation.0 Z Zero flag 0: Operation result is not “0”.1: Operation result is “0”.
