Chapter 16AppendixXVI - 10 Instruction Set MOVH (Am),DnMOVH (d8,Am),DnMOVH (d16,Am),DnMOVH (d32,Am),DnMOVH (d8,SP),DnMOVH (d16,SP),DnMOVH (d32,SP),DnMOVH (Di,Am),DnMOVH (abs16),DnMOVH (abs32),DnMOVH Dm,(An)MOVH Dm,(d8,An)MOVH Dm,(d16,An)MOVH Dm,(d32,An)MOVH Dm,(d8,SP)MOVH Dm,(d16,SP)MOVH Dm,(d32,SP)MOVH Dm,(Di,An)MOVH Dm,(abs16)MOVH Dm,(abs32)MOVM (SP),[reg1,.,regn]mem16(Am)(sign_ext) → Dnmem16(d8(sign_ext)+Am)(sign_ext) → Dnmem16(d16(sign_ext)+Am)(sign_ext) → Dnmem16(d32+Am)(sign_ext) → Dnmem16(d8(zero_ext)+SP)(sign_ext) → Dnmem16(d16(zero_ext)+SP)(sign_ext) → Dnmem16(d32+SP)(sign_ext) → Dnmem16(Di+Am)(sign_ext) → Dnmem16(abs16(zero_ext))(sign_ext) → Dnmem16(abs32)(sign_ext) → DnDm → mem16(An)Dm → mem16(d8(sign_ext)+An)Dm → mem16(d16(sign_ext)+An)Dm → mem16(d32+An)Dm → mem16(d8(zero_ext)+SP)Dm → mem16(d16(zero_ext)+SP)Dm → mem16(d32+SP)Dm → mem16(Di+An)Dm → mem16(abs16(zero_ext))Dm → mem16(abs32)PC+2 → PCmem32(SP) → reg,SP+4 → SPmem32(SP+4) → reg1,mem32(SP) → reg2,SP+8 → SPmem32(SP+8) → reg1,mem32(SP+4) → reg2,mem32(SP) → reg3,SP+12 → SPmem32(SP+12) → D2,mem32(SP+8) → D3,mem32(SP+4) → A2,mem32(SP) → A3,SP+16 → SPmem32(SP+28) → D0,mem32(SP+24) → D1,mem32(SP+20) → A0,mem32(SP+16) → A1,mem32(SP+12) → MDR,mem32(SP+8) → LIR,mem32(SP+4) → LAR,SP+32 → SPmem32(SP+32) → reg,mem32(SP+28) → D0,mem32(SP+24) →D1,mem32(SP+20) →A0,mem32(SP+16) →A1,mem32(SP+12) →MDR,mem32(SP+8) →LIR,mem32(SP+4) →LAR,SP+36 →SPmem32(SP+36)→reg1, mem32(SP+32)→reg2,mem32(SP+28)→D0,mem32(SP+24)→D1,mem32(SP+20)→A0,mem32(SP+16)→A1,mem32(SP+12)→MDR,mem32(SP+8)→LIR,mem32(SP+4)→LAR,SP+40 →SP----------------------------------------------------------------------------------------------------------------345745734723463462362222222222232232231112112212123458910S1111002111034....>5 6Group Mnemonic Operation Machine Code NotesFlag CodeSizeCycle For-matMN1030/MN103S SERIES INSTRUCTION SET7 8 9 10 11 12 13 14VF CF NF ZFMOVHMOVM registers specified with regs = 0registers specified with regs = 1registers specified with regs = 2(*1)registers specified with regs = 3(*1)registers specified with regs = =4(*1)registers specified with regs = 7registers specified with regs = 8registers specified with regs = 9(*1)*1: registers specified with regn are returned in the order; D2, D3, A2 and A3 no matter when the assembler srites theseregisters. Skip the registers which is not specified.
