Chapter 5Interrupt ControllerV - 2 Overview5.1 OverviewThe interrupt controllers are comprised of reset interrupts, non-maskable interrupts (NMI), 9 external interruptpins, and 45 internal interrupts (peripheral function interrupts).5.1.1 FunctionsTable:5.1.1 Interrupt FunctionsInterrupt type Reset interrupt Non-maskable interrupt Level interruptStarting address 0x40000000 0x40000008 0x40000000+ interruptValue of vector tableInterrupt level - - Can be set levels from 0 to 6 byprogramInterrupt factor count 1 2 9 (external pin input)31 (internal peripheral function)Interrupt factorExternal RST pin inputSoftware resetPower supply voltagedetection resetWatchdog timer overflow interruptSystem error interruptExternal pin input,Interrupts by internal peripheralfunctionGenerated (request)operationDirect input to CPU core Input to the CPU core from theNMICR registerInput the interrupt highest prioritylevel to the CPU core by GnICRregister.Accept operationAlways accepts Always accepts Acceptance by the processor sta-tus register (PSW) and interruptcontrol register (GnICR).Machine cycles untilacceptedRefer to [11.3.1 OscillationStabilization Wait Opera-tion]Up to 14 cycles Up to 14 cyclesPWM status afteracceptanceAll flags are cleared to “0”. The interrupt mask level of PSWis cleared to “000”.Values of the interrupt level flag areset to the interrupt mask level inPSW (masking all interruptrequests with the same or the lowerpriority)
