Chapter 12Serial interface 0 and 1Control Registers XII - 512.2.2 Serial Interface Reception and Transmission RegistersSerial interface 0 and 1 each 8-bit data buffer register for transmission/reception.Data is loaded by reading data from the SCnRB register during serial reception.Reception data can be loaded when an interrupt occurs or when the SCnRXA flag of the SCnSTR register is “1”.In the case of 7-bit transmission, the MSB (bit 7) is “0”. Proper operation of this register is not guaranteed if datais written. If the register is read through 16-bit access, the reception flag in the status register is cleared.Data transmission is initiated by writing data to the SCnTB register during serial transmission.Data transmission starts during 4 transmit clock cycles from write. In the case of 7-bit transmission, the MSB (bit7) is ignored.■ Serial 0 Reception Register (SC0RB: 0x0000A104) [8,16-bit Access Register]■ Serial 1 Reception Register (SC1RB: 0x0000A114) [8,16-bit Access Register]■ Serial 0 Transmission Register (SC0TB: 0x0000A10C) [8,16-bit Access Register]■ Serial 1 Transmission Register (SC1TB: 0x0000A11C) [8,16-bit Access Register]bp 7 6 5 4 3 2 1 0Flag SCA0RB7SCA0RB6SCA0RB5SCA0RB4SCA0RB3SCA0RB2SCA0RB1SCA0RB0At reset 0 0 0 0 0 0 0 0Access R R R R R R R Rbp 7 6 5 4 3 2 1 0Flag SCA1RB7SCA1RB6SCA1RB5SCA1RB4SCA1RB3SCA1RB2SCA1RB1SCA1RB0At reset 0 0 0 0 0 0 0 0Access R R R R R R R Rbp 7 6 5 4 3 2 1 0Flag SCA0TB7SCA0TB6SCA0TB5SCA0TB4SCA0TB3SCA0TB2SCA0TB1SCA0TB0At reset 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/Wbp 7 6 5 4 3 2 1 0Flag SCA1TB7SCA1TB6SCA1TB5SCA1TB4SCA1TB3SCA1TB2SCA1TB1SCA1TB0At reset 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/W
