Chapter 6ROM CorrectionVI - 6 ROM Correction Control Registers■ ROM Correction 2 Address Register (RCR2AR: 0x7FF00120) [32-bit access register]■ ROM Correction 3 Address Register (RCR3AR: 0x7FF00130) [32-bit access register]bp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Flag RC2CEN- - - - - - - - - - - RC2AD19RC2AD18RC2AD17RC2AD16At reset 0 0 0 0 0 0 0 0 0 0 0 0 x x x xAccess R/W R R R R R R R R R R R R/W R/W R/W R/Wbp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Flag RC2AD15RC2AD14RC2AD13RC2AD12RC2AD11RC2AD10RC2AD9RC2AD8RC2AD7RC2AD6RC2AD5RC2AD4RC2AD3RC2AD2RC2AD1RC2AD0At rest x x x x x x x x x x x x x x x xAccess R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/Wbp Flag Description Set condition31 RC2CEN ROM correction channel 2 enabled 0: ROM correction disabled1: ROM correction enabled30-20 - - -19-0RC2AD19toRC2AD0ROM correction channel 2 address These bits specify the lower 20 bits of the ROM address subject toROM correction. 8 bytes of data from the above ROM address to(ROM address + 7) are subject to ROM correction.bp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Flag RC3CEN- - - - - - - - - - - RC3AD19RC3AD18RC3AD17RC3AD16At reset 0 0 0 0 0 0 0 0 0 0 0 0 x x x xAccess R/W R R R R R R R R R R R R/W R/W R/W R/Wbp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Flag RC3AD15RC3AD14RC3AD13RC3AD12RC3AD11RC3AD10RC3AD9RC3AD8RC3AD7RC3AD6RC3AD5RC3AD4RC3AD3RC3AD2RC3AD1RC3AD0At reset x x x x x x x x x x x x x x x xAccess R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/Wbp Flag Description Set condition31 RC3CEN ROM correction channel 3 enable 0: ROM correction disabled1: ROM correction enabled30-20 - - -19-0RC3AD19toRC3AD0ROM correction channel 3 address These bits specify the lower 20 bits of the ROM address subject toROM correction. 8 bytes of data from the above ROM address to(ROM address + 7) are subject to ROM correction.
