Chapter 4Bus ControllerOperation IV - 5■ Store BufferThe bus controller has one store buffer (with a 32-bit data width) to avoid time penalty when conducting storageoperation in internal I/O. The CPU storage operation is completed when the address, data and access size arestored in the store buffer, and is executed with no wait states. Writes from the store buffer to the internal I/O areconducted in parallel with subsequent CPU operations. However, if there is a request from the CPU for loading orstoring to the internal I/O before writing from the store buffer is completed, execution of the request is delayed.4.2.2 Internal ROM access control registerThe internal ROM and internal flash memory can access in 2 cycles when the CPU clock (MCLK) is under 40MHz.Access cycle is set by the ROM access control register (ROMCTR).■ Internal ROM Access Control Register (ROMCTR: 0x00008078) [16-bit Access Register]bp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Flag - - - - ReservedReservedROMWC1ROMWC0 - - - ReservedReservedReserved - -At reset 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0Access R R R R R/W R/W R/W R/W R R R R R R R Rbp Flag Description Set condition15-12 - - -11-10 Reserved Reserved Always set “00”9-8 ROMWC[1:0] Set the internal ROM access cycle count00: Setting prohibited01: 2 cycle(2 ×MCLK) accessIf CPU clock (MCLK) becomes 40 MHz or over, it is prohibited.10: 3 cycle(3 ×MCLK) accessWhen the CPU clock (MCLK) is 40 MHz or over, change an accessto the internal ROM to 3 cycle access (ROMMC[1:0]=10) by theinternal ROM access control register (ROMCTR) before thePLLSEL flag of the PLL control register (PCNT) is switched from"0" to "1".The operation that is set to 2 cycle access is not guranteed.11: Setting prohibited7-5 - - -4-2 Reserved Reserved Always set “001”1-0 - - -
