Chapter 13Serial Interface 2Operation XIII - 15■ Last Bit of Transmission DataTable: 13.3.4 shows the last bit data output holding period at transmission and minimum data input period of thelast bit at reception. At slave, an internal clock should be set to secure data holding time at data transmission.Table:13.3.4 Last Bit Data Length of Data TransferWhen no start condition is specified (SC2STE flag = 0), the SBO2 output after the last bit data output holdingperiod can be set with the SC2FDC1-0 flags of the SC2CTR3 register as shown in Table: 13.3.5.After reset is released, the output prior to serial transfer is “H” regardless of the setting value of the SC2FDC1-0flags. When a start condition is specified (SC2STE), “H” is output regardless of the setting value of the SC2FDC1to 0.Table:13.3.5 SBO2 Output After Last Bit Data Output Holding Period (without start condition)■ Setting Other Control FlagsThe following flags need not be set or monitored because they are not used for clock synchronous communica-tion.Table:13.3.6 Other Control FlagsLast bit data holding period at transmission Last bit data input period at receptionAt master 1-bit data length1 bit data length (min.)At slave [1-bit data length of external clock × 1/2]+[Internal clock cycle × (1/2 to 3/2)]SC2FDC1 flag SC2FDC0 flag SBO2 output after last bit dataoutput holding period0 0 Fixed to "1"(High) output1 0 Fixed to "0"(Low) outputX 1 Last data retainedRegister Flag Description0SC2CTR2SC2BRKE Break status transmission controlSC2BRKF Break status reception monitorSC2NPE Parity enableSC2PM1 to 0 Additional bit specificationSC2FM1 to 0 Frame mode specificationSC2STRSC2PEK Parity error detectionSC2FEF Frame error detection
