Chapter 10Motor Control PWMX - 24 Operation■ Dead TimeDead Time is designed to insert on time delay into each of the upper and lower phases when the signal is invertedat each PWM output phase. The DTEN flag of the PWMMDn register is used to select whether to enable or dis-able dead time. The ORMDn flag of the PWMMDn register is used to select output logic at the time of dead timeinsertion. The dead time setting register (DTMSETn) is used to specify delay time inserted as dead time. Any of“00” to “FF” can be selected as dead time with 8-bit data. The dead time counter functions in synchronizationwith MCLK when the CLKSELn flag of the PWMMDn register is “1” and with IOCLK when it is “0”, and countsby 1 every 2 clock cycles. Calculate the dead time or delay time based on “set value × 2+1”. Thus, when “00” isspecified, 1 clock cycle of dead time is inserted if dead time is enabled.Figure:10.3.4 Dead TimeWAVEMDn = 0Dead time insertion logic (ORMDn = 0) Dead time insertion logic (ORMDn = 1)Period settingValue to becomparedPeriod settingValue to becomparedPWMxxNPWMxxPWMxxNPWMxxPWM count valuePWM basic waveformPWM output waveformPWM count valuePWM basic waveformPWM output waveformPWM count valuePWM basic waveform PWM basic waveformPWM output waveform PWM output waveformPWM count valuePWM output polarity (PXDTn, PXDTNn = 0)PWM output polarity (PXDTn, PXDTNn = 1)Dead time insertion enable/disable (DTENn = 1: enabled/0: disabled)Dead time count value (DTMSETn = 8 bits)
