Chapter 16AppendixXVI - 48 Extension Instruction SpecificationMULQU (unsigned high-speed multiply instruction: register to register)[Instruction format (macro name)]MULQU Dm, Dn[Assembler mnemonic]udf01 Dm, Dn[Operation]This instruction performs high-speed multiply operation by means of the multiplier provided in the extensionarithmetic unit.The instruction multiplies the content of Dm (unsigned 32-bit integer: multiplicand) by the content of Dn(unsigned 32-bit integer: multiplier) and stores high-order 32 bits and low-order 32 bits of the 64-bit resultrespectively in the high-speed multiply register MDRQ and Dn.The instruction determines the range within which the multiplier stored in Dn is significant (determination ismade starting LSB and in units of 2 bytes) before performing operation. Only the range within which a significantvalue is contained is subject to multiply operation. That is, the smaller the content of Dn, the faster the operationresult is obtained.[Flag changes][Note for programming]Updating of the PSW as a result of flag changes is delayed by 1 instruction.Note, however, that flags can be evaluated for the Bcc and Lcc instructions before flag changes are reflected in thePSW.Flag Change ConditionV * UndefinedC * UndefinedN + "1" if the MSB of the low-order 32 bits of the result is "1." "0" in any other case.Z + "1" if the low-order 32 bits of the result are "0s." "0" in any other case.
