Chapter 916-bit TimerControl registers IX - 25■ Timer 13 Mode Register (TM13MD: 0x0000A2A0) [8, 16-bit Access Register]bp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Flag TMXF- TMTGETMONETMCLETMCGETMUD1TMUD0TMCNETMLDE- - - TMCK2TMCK1TMCK0At reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0Access R R R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/Wbp Flag Description Setting condition15 TMXF Timer operation display 0: Timer stopping1: Timer operating14 - - -13 TMTGETimer external trigger enable 0:Timer activation disabled by PWM11: Timer activation enabled by PWM1When timer activation is enable by PWM1, set the activation triggerpolarity selection of the timer 13 compare A mode register to “1”.12 TMONETimer 1-shot operation enable 0 : 1-shot operation disabled (Timer does not stop.)1: 1-shot operation enabled (Timer stops when the TMBC and theTMCA match.)11 TMCLETimer binary counter enable 0: Clear operation disabled1: Clear operation enabledWhen the TMCA is set to a compare registerTMBC is cleared when the TMBC and the TMCA match.When the TMCA is set to a capture registerTMBC is cleared when captured to TMCA.10 TMCGE Reserved Always set to “0”9-8 TMUD1TMUD0Up/down counting selection 00: Up counting01: Down counting10: Setting prohibited11: Setting prohibited7 TMCNE TImer operation enable 0: Operation disabled1: Operation enabled6 TMLDETimer initialization 0: Normal operation1: InitializationTMBC=0x0000When the TMCA and TMCB are set to the compare register of thedouble buffer, the value is loaded into the compare register from thebuffer. Pin output is initialized.5-3 - - -2-0TMCK2TMCK1TMCK0Timer count clock source selection 000: IOCLK, MCLK001: IOCLK/8, MCLK/8010: Timer 6 underflow011: Timer 7 underflow100: Setting prohibited101: Setting prohibited110: Setting prohibited111: Setting prohibitedWhen using IOCLK/8, operation must be enabled by the prescalercontrol registers (TMPSCNE).When using MCLK, select MCLK by the clock source selection reg-ister ( TMnCLK).
