Chapter 16AppendixExtension Instruction Specification XVI - 59MACIHU (unsigned halfword data multiply and accumulate instruction: immediate to register)[Instruction format (macro name)]MACIHU imm, Dn[Assembler mnemonic]udfu31 imm8, Dn : imm8 is 0-extendedudfu31 imm16, Dn[Operation]This instruction performs multiply and accumulate operation by means of the multiplier and adder provided in theextension arithmetic unit.The instruction multiplies 16-bit data (multiplicand), obtained by 0-extending imm, by the content of Dn(unsigned 16-bit integer: multiplier), adds this product to the 64-bit accumulative sum whose high-order 32 bitsand low-order 32 bits are stored respectively in the multiply and accumulate registers MCRH and MCRL andstores high-order 32 bits and low-order 32 bits of the 64-bit result respectively in the multiply and accumulateregisters MCRH and MCRL.The register outputs a multiply and accumulate overflow detection flag “1” to the register MCVF if theaccumulative sum data overflows beyond 64 bits during addition of the product and the accumulative sum.[Flag changes][Note for programming]An instruction other than extension instructions that requires 1 or more cycles must be inserted between thisinstruction and a next extension instruction.Flag Change ConditionV -C -N -Z -
