Chapter 88-bit TimerVIII - 44 Cascade Connection■ Selecting the Count SourceSelect any desired count source for the lowest-order timer. Set the count clock source for high-order timers (except the lowest-order timer) to “cascading”.For example, when using timers 0 and 1 as a 16-bit timer, set a desired count clock source for timer 0 and thecount clock source for timer 1 to “cascading”. When using timers 1, 2 and 3 as a 32-bit timer , set a desired countclock source for timer 0 and the count clock source for timer 1 to “cascading”.■ Setting the Timer Base RegisterSet a timer division ratio in timer base register (TMnBR).Timer interrupt cycle = (TMnBR setting + 1) × Count clock source cycleFor example, when using timers 0 and 1 as a 16-bit timer and setting the interrupt cycle to “0x2000”,“0x1FFF(0x2000-1)” should be set the TMnBR register. Set “0x1F” to the upper TM1BR register and “0xFF” tothe lower TM0BR register. It is possible to set the TMnBR register by 16-bit access simultaneously when usingtimer 1 + timer 0, timer 3 + timer 2, timer 5 + timer 4, timer 7 + timer 6, timer 15 + timer 14 or timer 17 + timer16 as a 16-bit timer. (Not when timer 2 + timer 1, timer 6 + timer 5 and timer 16 + timer 15 are cascaded as a 24-bit timer or 32-bit timer.)■ Initializing the timerSet the TMnLDE flags of all cascaded timers to “1” to initialize the timers. (It is not necessary to set all registersat the same time.)■ Enabling Counting OperationWhen enabling timer counting operation, enable the counting operation of the cascaded timers in sequence start-ing from the highest-order timer, or enable the counting operation for all of the cascaded timers simultaneously.■ Stopping Counting OperationWhen stopping timer counting operation, stop the counting operation of the cascaded timers in sequence startingfrom the lowest-order timer, or stop the counting operation for all of the cascaded timers simultaneously.■ Timer OutputsThe timer output from the highest of the cascaded timers can be used. Operation of the timer output from thelower cascaded timers is not guaranteed.■ Interrupt RequestsThe interrupt requests from the highest of the cascaded timers can be used. The interrupt requests from the lowercascaded timers are not generated, but set timers to interrupts disabled.■ Changing the Time Base Register during Counting OperationWhen timer 1 + timer 0, timer 3 + timer 2, timer 5 + timer 4, timer 7 + timer 6 , timer 15 + timer 14, or timer 17+ timer 16 are used as a 16-bit timer, the TMnBR register during counting operation can be changed via 16-bitaccess.When using other combination as a 16-bit timer or 32-bit timer, avoid load timing to the binary counter...Combined 8-bit access registers can be used with 16-bit access at cascade connection.(when the addresses of the registers are consecutive)..
