Chapter 16AppendixXVI - 16 Instruction Set BEQ (d8,PC)BNE (d8,PC)BGT (d8,PC)BGE (d8,PC)BLE (d8,PC)BLT (d8,PC)BHI (d8,PC)BCC (d8,PC)BLS (d8,PC)BCS (d8,PC)BVC (d8,PC)BVS (d8,PC)BNC (d8,PC)BNS (d8,PC)BRA (d8,PC)LEQLNEIF (ZF=1), PC + d8(sign_ext)→ PCIF (ZF=0),PC + 2 → PCIF (ZF=0), PC + d8(sign_ext) → PCIF (ZF=1), PC + 2 → PCIF ((ZF | (NF^VF))=0),PC + d8(sign_ext) → PCIF ((ZF | (NF^VF))=1),PC + 2 → PCIF ((NF ^ VF)=0),PC + d8(sign_ext) → PCIF ((NF ^ VF)=1),PC + 2 → PCIF ((ZF | (NF^VF))=1),PC + d8(sign_ext) → PCIF ((ZF | (NF^VF))=0),PC + 2 → PCIF ((NF ^ VF)=1),PC + d8(sign_ext) →PCIF ((NF ^ VF)=0),PC + 2 → PCIF ((CF | ZF)=0),PC + d8(sign_ext) → PCIF ((CF | ZF)=1),PC + 2 →PCIF (CF = 0),PC + d8(sign_ext) → PCIF (CF = 1),PC + 2 → PCIF ((CF | ZF)=1),PC + d8(sign_ext) → PCIF ((CF | ZF)=0),PC + 2 → PCIF (CF = 1),PC + d8(sign_ext) → PCIF (CF = 0),PC + 2 → PCIF (VF = 0),PC + d8(sign_ext) → PCIF (VF = 1),PC + 3 → PCIF (VF = 1),PC + d8(sign_ext) → PCIF (VF = 0),PC + 3 → PCIF (NF = 0),PC + d8(sign_ext) → PCIF (NF = 1),PC + 3 → PCIF (NF = 1),PC + d8(sign_ext) → PCIF (NF = 0),PC + 3 → PCPC + d8(sign_ext) →PCIF (ZF=1), LAR - 4 →PCIF (ZF=0),PC + 1 →PCIF (ZF=0), LAR - 4 →PCIF (ZF=1), PC + 1 →PC--------------------------------------------------------------------222222222233332113/1*3/1*3/1*3/1*3/1*3/1*3/1*3/1*3/1*3/1*4/2*4/2*4/2*4/2*31/2*1/2*S1S1S1S1S1S1S1S1S1S1D1D1D1D1S1S0S0111001100110011001100110011001100110011001111111111111111110011011101210001001000100100011000001010110011101001000100010001000101010001001311101110111011104....>....>....>....>....>....>....>....>....>....>1000100110101011....>56....>....>....>....>Group Mnemonic Operation Machine Code NotesFlag CodeSizeCycle For-matMN1030/MN103S SERIES INSTRUCTION SET7 8 9 10 11 12 13 14VF CF NF ZFBranch InstructionsBccLccBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disableBranch enable/disable*:Depends on the status of Instruction queue.