Chapter 13Serial Interface 2XIII - 14 Operation■ Setting Edge for Output/InputThe SC2CE1 flag of the SC2CTR0 register sets the edge of transmission data output and the edge of receptiondata input. Transmission data is output in synchronization with the falling edge of the clock when the SC2CE1flag = “0” and with the rising edge of the clock when the SC2CE1=”1”. Reception data is fed in synchronizationwith the rising edge of the clock when the SC2CE1 flag =”0” and with the falling edge of the clock when theSC2CE1=”1”.Table:13.3.2 Edge for Transmission Data Output/Reception Data Input■ Setting ClockA clock source is selected by the SC2PSC2 to 0 of the SC2CTR3 register and the SC2CKS1 to 0 of the SIFCLKregister. The dedicated prescaler is started to operate with selecting “prescaler operation” by the SC2PSCE flag ofthe SC2CTR3 register. The SC2MST flag of the SC2CTR1 register selects an internal clock (clock master) orexternal clock (clock slave). When selecting an external clock, set an internal clock whose clock cycle does notexceed and is similar to an external clock’ by the SC2CKS register. The reason for this is that the interrupt flagSC2TIRQ is generated by the internal clock. Table: 13.3.3 shows the internal clock source which can be set withthe SC2CKS register. Also, the internal clock can be set to 16 dividing further by the SC2CKM flag of theSC2CTR1 register.Table:13.3.3 Synchronous Serial Interface Internal Clock Source..Set the SC2SBIS and SC2SBOS flags of the SC2CTR1 register to “0” before switching clocksettings...■ Setting Parity CheckNo need for setting parity bit because it is not added.SC2CE1 Edge for transmission data output Edge for reception data input01Clock source Serial 2Internal clock1/2 of timer underflow1/4 of timer underflow1/16 of timer underflow1/64 of timer underflowIOCLK/2IOCLK/4
