Chapter 14A/D ConverterXIV - 36 Operation(4) Set the AD0: Set the AN0CTR0 registerSet the operation modeAN0CTR0(0x0000A400)bp1-0: AN0MD1-0=01Set the conversion clockAN0CTR0(0x0000A400)bp4-2: AN0CK2-0=011Set the conversion start channelAN0CTR0(0x0000A400)bp10-8: AN0CH2-0=000Set the conversion complete channelAN0CTR1(0x0000A404)bp14-12: AN0NCH2-0=010Set the power-down modeAN0CTR0(0x0000A400)bp6: AN0OFF=1(4) Set the AN0MD1-0 flags of the AN0CTR0 register to “01”to set “multiple channels/one-timer conversion” tooperation mode.Set the AN0CK2-0 flags of the AN0CTR0 register to“011” to set the conversion clock to4 dividing of IOCLK.Set the AN0CH2-0 flags of the AN0CTR0 register to“000” to set “channel 0” to the conversion channel.Set the AN0NCH2-0 flags of the AN0CTR0 register to“010” to set “channel 2) to the last channel to beconverted.Set the AN0OFF flag of the AN0CTR0 register to “1” toset operation mode to the power-down mode flag.*After shifted to operation mode, more than 100nsecwait time is necessary until A/D conversion start.(5) Set the AD0: Select the AD0 start triggerADST0(0x0000A408)bp2-0: AD0ST2-0=010(5) Set the AD0ST2-0 flags of the A/D start selectionregister (ADST0) to “010” to start the A/D conversion bythe timer 12 compare A interrupt.(6) Set the external trigger conversion startenabledAN0CTR0(0x0000A400)bp5: AN0TRG=1(6) Set the AN0TRG flag of the AN0CTR0 register to “1” toset conversion start by the timer 11 compare Ainterrupt.(7) Set the AD0: Set the interrupt levelG26ICR(0x00008968)bp14-12: G26LV2-0=100(7) Set the AD0 complete interrupt level by the G26LV2-0flags of the G26ICR register. When the interruptrequest flag is already set, clear the request flag.(8) Set the AD0: Enable the interruptG26ICR(0x00008968)bp8: G26IE0=1(8) Set the G26IE0 flag of the G26ICR register to “1” toenable the AD0 complete interrupt.(9) Set the timer 12: Select the cycleTM12CA(0x0000A288)=0x752F(9) Set the cycle to the timer 12 compare/capture A register(TM12CA). Due to 30000 dividing, the set value is29999 (0x752F).(10) Set the timer 12: Set the count clock sourceTM12MD(0x0000A280)bp2-0: TMCK2-0=000(10) Select the count clock source (IOCLK) by the TMCK2-0flags of the TM12MD register.(11) Set the timer 12: Select up/downTM12MD(0x0000A280)bp9-8: TMUD1-0=00(11) Select the timer up counting by the TMUD1-0 flags ofthe TM12MD register.(12) Set the timer 12: Set the counter clearenabledTM12MD(0x0000A280)bp11: TMCLE=1(12) Set the TMCLE flag of the TM12MD register to “1” toenable the clear operation of the TM11BC counter.When the TM12CA register and the TM12BC countermatch, the TM12BC counter is cleared.Setup Procedure Description
