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North Atlantic 68C3 manuals

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68C3

Brand: North Atlantic | Category: I/O Systems
Table of contents
  1. MODEL 68C3
  2. GENERAL BOARD SPECIFICATION
  3. SOFTWARE SUPPORT
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. SPECIFICATIONS
  22. RS-422/485 (Module PC) – Isolated, Four High Speed RS-422 / 485 Serial Communications
  23. A/D (Module C1) – Ten A/D Channels (1.25 to 10.0 VDC FS) Uni or Bipolar
  24. A/D (Module C2) – Ten A/D Channels (5.0 to 40.0 VDC FS) Uni or Bipolar
  25. A/D (Module C3) – Ten A/D Channels (4-25mA)
  26. A/D (Module C4) – Ten A/D Channels (6.25 to 50.0 VDC FS) Uni or Bipolar
  27. Specifications applicable to channels 1-6 (40 VDC A/D)
  28. I/O (Module D7) – Sixteen TTL Channels— Programmable for I/O
  29. D/A (Module F1) − Ten D/A Outputs (  10 VDC)
  30. D/A (Module F5) − Four D/A High Current Outputs (  20VDC at 100 mA)
  31. D/A (Module J5) − Ten D/A Outputs (  2.5 VDC)
  32. RTD (Module G4) – Six Channel RTD Measurement
  33. Features
  34. A/D Channels
  35. S/D (Module S*) – Four Isolated Synchro/Resolver Measurement Channels
  36. D/S (Module 6*) –Three Isolated Digital-to-SYN/RSL Ch, 0.25 VA Power Output
  37. DLV (Module 5*) – Three Isolated DLV Stimulus Channels, LVDT or RVDT Outputs
  38. SSI Mode
  39. Input
  40. C3 ADDRESS CONFIGURATION
  41. PRODUCT CONFIGURATION AND MEMORY MAP
  42. C3 CARD-LEVEL MODULE CONFIGURATION and MEMORY MAPPING
  43. ARINC 429/575 SIX CHANNEL, TX/RX (MODULE A4)
  44. Receive Operation
  45. Schedule Transmit Commands
  46. Interrupt
  47. Module Factory Defaults
  48. Tx (Transmit) Buffer (FIFO)
  49. Rx FIFO (Buffer) Threshold
  50. Channel Control Low
  51. Channel Control High
  52. Channel Status
  53. Interrupt Enable
  54. Interrupt Status
  55. Mailbox (MBOX) Address Register
  56. Mailbox (MBOX) Data Register
  57. Transmit Trigger Register
  58. Transmit Stop Register
  59. Timestamp Hi + Lo Register
  60. Memory Page Window
  61. Rx Match Memory Layout
  62. DSP Compile Time
  63. MODULE PCI MEMORY MAP – 6 CHANNEL ARINC COMMUNICATIONS (A4)
  64. COMMUNICATIONS (MODULES N7 AND N8)
  65. CANBUS CONTROL AREA NETWORK (MODULE P6, PA)
  67. P6 Specific CAN A/B Register Descriptions
  68. Acceptance Mask LO (set per channel) (P6 – CAN A/B Only)
  69. MSG_ID3
  70. Data Size
  71. PA Specific J1939 Register Descriptions
  72. P6 (CAN A/B) or PA (J1939) Global Register Descriptions
  73. Comm Status for Channel X (Global)
  74. Ch X Baud / Bit Timing Register (Global)
  75. Ch X Baud Rate Prescaler Extension Reg (Global)
  76. PGN_HI (Global)
  77. MODULE (P6) CANBUS CAN A/B PCI REGISTER MAP
  78. MODULE (PA) CANBUS J1939 PCI REGISTER MAP
  79. FOUR CHANNEL, SERIAL (RS232/422/485) (MODULE P8) / ISOLATED RS-422/RS-485 (MODULE PC)
  80. Serial Communications Specifications
  81. Communication Module Factory Defaults: Registers and Delays
  82. Transmit Buffer
  83. Number of Words Rx Buffer
  84. Interface Levels
  85. Tx-Rx Configuration Low
  87. Channel Control Extended
  88. Baud Rate
  89. Rx Buffer Almost Full
  90. Rx Buffer Low Watermark
  91. HDLC Tx Address/Sync Character
  92. XOFF Character
  96. FOUR CHANNEL SERIAL COMMUNICATIONS (MODULE P8/PC) PCI MEMORY MAP
  97. A/D (MODULES C1, C2, C3, C4 & CA)
  98. Data Read
  99. D0 Test Voltage
  100. FIFO Size (per channel)
  101. Trigger Control (per channel)
  102. Software Trigger (per channel)
  103. Test Enable
  104. Open Status
  105. Interrupt and Status Register Operation/Clarification
  106. A/D (MODULES C1, C2, C3 & C4) PCI MEMORY MAP
  107. I/O DIGITAL TTL/CMOS (MODULE D7)
  108. Read Input or Output
  109. Reset Over-Current
  111. I/O DIGITAL TTL/CMOS (MODULE D7) PCI MEMORY MAP
  112. DIFFERENTIAL MULTI-MODE TRANSCEIVERS (MODULE D8)
  113. De-bounce Time
  114. Input/Output Format
  115. Interrupt Vectors
  117. I/O (MODULE D8) PCI MEMORY MAP
  118. D/A (MODULES F & J, EXCEPT J8)
  119. D/A Polarity
  120. Over Current Override
  121. Words in FIFO
  122. Sample Rate
  123. Trigger Control
  125. Over Current Status
  127. D/A (MODULE F OR J, EXCEPT J8) PCI MEMORY MAP
  128. HIGH VOLTAGE D/A (MODULE J8)
  129. D/A Output Range
  131. BIT Status Interrupt Enable
  133. D/A (MODULE J8) PCI MEMORY MAP
  134. THERMOCOUPLE MEASUREMENT (MODULE G3)
  135. Temperature
  136. ADC Data (RAW)
  137. Compensation Type
  138. Update Rate
  141. Appendix A (IEEE 754 Format)
  142. Appendix B (G3 Optional External Isothermal Block Accessory)
  143. Optional Accessory NAI P/N ACC-ISO-THERM-BLK1
  144. THERMOCOUPLE (MODULE G3) PCI MEMORY MAP
  145. RTD (MODULE G4)
  146. Resistance
  147. Wire Lead Resistance Compensation
  150. RTD (MODULE G4) PCI MODULE REGISTER MAP
  151. LOAD/STRAIN (MODULE G5)
  152. data2.
  153. Range
  154. Chop Enable
  155. Filter Configuration
  156. BUSY
  157. Open Status Interrupt Enable
  159. Appendix (G5)
  160. STRAIN GAGE (MODULE G5) PCI MODULE MEMORY REGISTER MAP
  161. I/O DISCRETE (MODULE K6 VER. 4 )
  163. Threshold Programming
  164. Upper Threshold
  165. Read I/O
  166. Current for Source/Sink
  167. Write Output
  168. Read Output Voltage
  171. I/O Discrete (Module K6) – Addendum A (PWM Enhanced Function)
  172. PWM/Timer Period
  173. PWM/TIMER Configuration (Polarity)
  174. PWM/TIMER Mode Enable
  175. DISCRETE (MODULE K6 VER. 4) PCI MODULE MEMORY REGISTER MAP
  176. I/O DISCRETE (MODULE K7)
  177. Input/Switch Interface
  178. Max High Threshold
  180. Read Switch Current (Average)
  183. DISCRETE (MODULE K7) PCI MODULE MEMORY REGISTER MAP
  184. I/O RELAY (MODULE KN, KL)
  185. Status, BIT Fault
  187. I/O RELAY (MODULE KN, KL) PCI MEMORY MAP
  188. DISCRETE/ANALOG TO DIGITAL COMBINATION (MODULE KA)
  189. KA Module A/D Specific Functions
  190. KA Module Discrete I/O Specific Functions
  194. Status Interrupt Enable
  196. DISCRETE / A-D COMBINATION (MODULE KA) PCI MEMORY MAP
  197. LVDT MEASUREMENT (MODULE L*)
  198. Various LVDT Configurations
  199. Bandwidth (BW)
  201. Input Reference Frequency Measurement
  202. Reference Status
  203. OSC (Onboard) Excitation Set Frequency
  204. Interrupt Vector
  205. Hi-Threshold
  206. Buffer Data Type
  207. Status, BIT Fail
  209. LVDT (MODULE L) PCI MEMORY MAP
  210. SYNCHRO/RESOLVER MEASUREMENT (MODULE S*)
  211. Data
  212. Bandwidth Select
  213. Test (D2) Verify
  214. Angle Δ
  215. A & B Resolution
  216. Signal Status
  217. Signal Status Interrupt Enable
  218. S/D Angle Change (Angle Δ Alert) Interrupt Enable
  220. Low-Threshold
  221. Trigger Mode
  223. S/D (MODULE S) PCI MEMORY MAP
  224. D/S THREE CHANNEL (MODULE 6*)
  225. Signal Loss Threshold
  226. D/S Write Angle – Two Speed
  227. D/S Rotation Status
  228. D/S Ratio 1/2
  229. D/S Module Power Enable
  230. D/S Status, Phase Lock Loss
  231. Reference Loss Interrupt Enable
  232. OSC (Optional Onboard Reference Supply) Set Voltage
  234. D/S 3 CHANNEL (6*) PCI MODULE MEMORY MAP
  235. DLV 3 CHANNEL (MODULE 5*)
  236. DLV Channel Signal Voltage
  237. Status, Signal Loss
  239. DLV Module Power Enable
  240. DLV Status, Excitation
  242. DLV Status, BIT Test
  243. Phase Lock Loss Interrupt Enable
  245. CH DLV (5*) (PCI) MODULE MEMORY MAP
  246. SSI / ENCODER / QUADRATURE COUNTER (MODULE E7)
  247. Channel Inputs
  248. Standard SSI Interface Controller Mode
  249. Listen Only Mode
  250. Parity
  251. Control Register 0
  252. Control Register 1
  253. SSI Status
  254. Counter Modes
  255. Index Control Modes (ICM)
  256. Special Count Mode
  257. Internal Clock Prescaler
  258. Counter Status Register
  259. Up/Down Count
  260. Interval Timer Control
  261. Global Control Registers
  262. Multiple Channel Read
  264. Interrupt Enable Register
  265. CPLD (Module Configuration Registers)
  266. CPLD Register Low
  267. Differential (DE) / Single-Ended (SE) Selection
  268. Appendix A – Quadrature (A-Quad-B) Discussion
  269. Appendix B – Operation Mode Signal Details
  270. FOUR CHANNEL SSI/ENCODER (MODULE E7) PCI MEMORY MAP
  271. ISOLATED ±15V DC/DC CONVERTER (MODULE V1, V2)
  272. Registers
  273. Output Current (V-)
  275. MODULE (V*), DUAL ±15V DC/DC CONVERTER, PCI MEMORY REGISTER MAP
  276. REFERENCE (MODULE W*)
  277. Reference Voltage
  278. REFERENCE (MODULE W*) PCI MEMORY MAP
  279. MODULE IDENTIFICATION
  280. Module FPGA Revision
  281. GENERAL USE REGISTER MEMORY MAP
  282. Platform
  283. Date Code
  284. Board Ready
  285. Design Version
  286. Customer Defined Register Allocation
  287. ETHERNET
  288. Type Codes Summary
  289. C3 CONNECTOR/PIN-OUT INFORMATION
  290. Front Panel (J1, J2) (Connector Placement and Orientation)
  291. Rear I/O VPX Connectors P0 – P2
  292. Rear I/O Utility Plane (P0)
  293. Rear I/O Data/Control Planes (P1 Continued)
  294. Rear I/O Summary
  295. SLOT 1 – Analog and Digital I/O Modules (User Defined I/O Pin-Outs)
  296. SLOT 1 –Digital I/O Modules (User Defined I/O Pin-Outs)
  297. SLOT 1 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)
  298. SLOT 1 – Communications I/O Modules (User Defined I/O Pin-Outs)
  299. SLOT 2 – Analog I/O Modules (User Defined I/O Pin-Outs)
  300. SLOT 2 –Digital I/O Modules (User Defined I/O Pin-Outs)
  301. SLOT 2 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)
  302. SLOT 2 – Communications Modules (User Defined I/O Pin-Outs)
  303. SLOT 3 – Onboard Reference or Multi-Function Combo (User Defined I/O Pin-Outs)
  304. Connector Signal/Pin-Out Notes
  305. PART NUMBER DESIGNATION
  306. Part Number Notes
  307. Channel D/S Module Code Table
  308. Channel DLV Module Code Table
  309. REVISION
  310. 68C3 Operations Manual
North Atlantic categories
Measuring Instruments
Handsets
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Laboratory Equipment
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