Table 10-3. Instruction Set Summary (continued)Source Form Operation DescriptionEffect on CCRAddressModeOpcodeOperandBus CyclesV H I N Z C– – – – – – DIR (b3) 16 dd 5BSET n,opr8a Set Bit n in Memory Mn ← 1 – – – – – – DIR (b4) 18 dd 5– – – – – – DIR (b5) 1A dd 5– – – – – – DIR (b6) 1C dd 5– – – – – – DIR (b7) 1E dd 5PC ← (PC) + 0x0002push (PCL)BSR rel Branch to Subroutine SP ← (SP) – 0x0001push (PCH)– – – – – – REL AD rr 5SP ← (SP) – 0x0001PC ← (PC) + relCBEQ opr8a,rel Branch if (A) = (M) – – – – – – DIR 31 dd rr 5CBEQA#opr8i,relBranch if (A) = (M) – – – – – – IMM 41 ii rr 4CBEQX#opr8i,relCompare and Branchif EqualBranch if (X) = (M) – – – – – – IMM 51 ii rr 4CBEQ oprx8,X+,relBranch if (A) = (M) – – – – – – IX1+ 61 ff rr 5CBEQ ,X+,rel Branch if (A) = (M) – – – – – – IX+ 71 rr 5CBEQoprx8,SP,relBranch if (A) = (M) – – – – – – SP1 9E61 ff rr 6CLC Clear Carry Bit C ← 0 – – – – – 0 INH 98 1CLI Clear Interrupt MaskBitI ← 0 – – 0 – – – INH 9A 1CLR opr8a M ← 0x00 0 – – 0 1 – DIR 3F dd 5CLRA A ← 0x00 0 – – 0 1 – INH 4F 1CLRX X ← 0x00 0 – – 0 1 – INH 5F 1CLRH Clear H ← 0x00 0 – – 0 1 – INH 8C 1CLR oprx8,X M ← 0x00 0 – – 0 1 – IX1 6F ff 5CLR ,X M ← 0x00 0 – – 0 1 – IX 7F 4CLR oprx8,SP M ← 0x00 0 – – 0 1 – SP1 9E6F ff 6CMP #opr8i ↕ – – ↕ ↕ ↕ IMM A1 ii 2CMP opr8a ↕ – – ↕ ↕ ↕ DIR B1 dd 3CMP opr16a ↕ – – ↕ ↕ ↕ EXT C1 hh ll 4CMP oprx16,X ↕ – – ↕ ↕ ↕ IX2 D1 ee ff 4CMP oprx8,X Compare Accumulatorwith Memory(A) – (M); (CCRUpdated But OperandsNot Changed)↕ – – ↕ ↕ ↕ IX1 E1 ff 3CMP ,X ↕ – – ↕ ↕ ↕ IX F1 3CMP oprx16,SP ↕ – – ↕ ↕ ↕ SP2 9ED1 ee ff 5Table continues on the next page...Instruction Set SummaryMC9S08SU16 Reference Manual, Rev. 5, 4/2017146 NXP Semiconductors
