The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel(n) match (FTM counter = CnVH:L) when the FTM counting is down, at the begin of thepulse width, and when the FTM counting is up, at the end of the pulse width.This type of PWM signal is called center-aligned because the pulse width centers for allchannels are aligned with the value of 0x0000.The other channel modes are not compatible with the up-down counter (CPWMS = 1).Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).pulse widthcounter overflowFTM counter =MODH:Lperiod2 x (CnVH:L)2 x (MODH:L)FTM counter =0x0000channel (n) match(FTM countingis down)channel (n) match(FTM countingis up)counter overflowFTM counter =MODH:Lchannel (n) outputFigure 19-14. CPWM period and pulse width with ELSnB:ELSnA = 1:0If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnVH:L registers,the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however thechannel (n) output is not controlled by FTM.If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)match (FTM counter = CnVH:L) when counting down, and it is forced low at the channel(n) match when counting up; see the following figure.TOF bit... 7 8 87 7 76 6 65 5 54 43 32 21 0 1 ...previous valueCNTH:Lchannel (n) outputcounteroverflowchannel (n) match indown counting channel (n) match inup countingchannel (n) match indown countingcounteroverflowCHnF bitMODH:L = 0x0008CnVH:L = 0x0005Figure 19-15. CPWM signal with ELSnB:ELSnA = 1:0If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)match (FTM counter = CnVH:L) when counting down, and it is forced high at thechannel (n) match when counting up; see the following figure.Chapter 19 FlexTimer Module (FTM)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 337
