The MTIM16 counter (CNTH:CNTL registers) has three modes of operation: stopped,free-running, and modulo. The counter is stopped out of reset. If the counter startswithout writing a new value to the modulo registers, it will be in free-running mode. Thecounter is in modulo mode when a value other than 0x0000 is in the modulo registers.After an MCU reset, the counter stops and resets to 0x0000, and the modulo also resets to0x0000. The bus clock functions as the default clock source, and the prescale value isdivided by 1. To start the MTIM16 in free-running mode, write to the MTIM16 statusand control (SC) register and clear the MTIM16 stop (TSTP) bit.Clock sources are software selectable:• the internal bus clock• the fixed frequency clock (XCLK)• an external clock on the TCLK pin that is selectable as incrementing on either risingor falling edgesThe MTIM16 clock select (CLKS) field in the CLK register selects the desired clocksource. If the counter is active (the TSTP bit is 0) when a new clock source is selected,the counter continues counting from the previous value using the new clock source.Nine prescale values are software selectable: clock source divided by 1, 2, 4, 8, 16, 32,64, 128, or 256. The prescaler select bits (PS[3:0]) in the CLK register select the desiredprescale value. If the counter is active (TSTP = 0) when a new prescaler value is selected,the counter continues counting from the previous value using the new prescaler value.The MTIM16 modulo register (MODH:MODL) allows the overflow compare value to beset to any value from 0x0001 to 0xFFFF. Reset clears the modulo value to 0x0000, whichresults in a free-running counter.When the counter is active (the TSTP bit is 0), it increases at the selected rate until thecount matches the modulo value. When these values match, the counter overflows to0x0000 and continues counting. The MTIM16 overflow flag (TOF) is set whenever thecounter overflows. The flag sets on the transition from the modulo value to 0x0000.Clearing TOF is a two-step process. The first step is to read the SC register while TOF isset. The second step is to write a 0 to TOF. If another overflow occurs between the firstand second steps, the clearing process is reset and TOF stays set after the second step isperformed. This will prevent the second occurrence from being missed. TOF is alsocleared when a 1 is written to TRST.The MTIM16 module allows for an optional interrupt to be generated whenever TOF isset. To enable the MTIM16 overflow interrupt, set the MTIM16 overflow interruptenable (TOIE) bit in the SC register. The TOIE bit should never be written to be 1 whileTOF is 1. Instead, TOF should be cleared first, and then the TOIE bit can be set to 1.Chapter 13 Modulo Timer (MTIM)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 215
