• The channels are in input capture mode (Input capture mode)• The channels outputs are zero• The channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0b00). See table"Mode, Edge, and Level Selection"The following figure shows the FTM behavior after the reset. At the reset (item 1), theFTM counter is disabled (see table "FTM Clock Source Selection"), its value is updatedto zero and the pins are not controlled by FTM (table "Mode, Edge, and LevelSelection").After the reset, the FTM should be configured (item 2). It is necessary to define the FTMcounter mode, the FTM counting limit (MODH:L registers value), the channels mode andCnVH:L registers value according to the channels mode.Because of this, you should write any value to CNTH or CNTL registers (item 3). Thiswrite updates the FTM counter with the value of 0x0000 and the channels output with itsinitial value (except for channels in output compare mode) (Counter reset).The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It isimportant to highlight that the pins are controlled only by FTM when CLKS[1:0] bits aredifferent from zero (table "Mode, Edge, and Level Selection").(1) FTM reset. . .0x00060x00050x00040x00030x0001 0x00080x0007XXXX 0x0000 0x0002FTM counterCLKS[1:0](4) write 0b01 to CLKS[1:0](3) write any value toCNTH or CNTL registers(2) FTM configuration channel (n) pin is controlled by FTMNote– Channel (n) is in high-true EPWM mode with 0 < C(n)VH:L < MODH:L– C(n)VH:L = 0x000500XX 01channel (n) outputFigure 19-17. FTM behavior after the reset when the channel (n) is in EPWM modeThe following figure shows an example when the channel (n) is in output compare modeand the channel (n) output is toggled when there is a match. In the output compare mode,the channel output is not updated to its initial value when there is a write to CNTH orCNTL registers (item 3).Reset overviewMC9S08SU16 Reference Manual, Rev. 5, 4/2017340 NXP Semiconductors
