NOTEUser software must disable the peripheral before disabling theclocks to the peripheral. When clocks are re-enabled to aperipheral, the peripheral registers need to be re-initialized byuser software.Address: 1800h base + Dh offset = 180DhBit 7 6 5 4 3 2 1 0Read CMP0 GDU_CMP ADC1 ADC0 IRQ 0 PDB KBIWriteReset 0 0 0 0 0 0 0 0SIM_SCGC2 field descriptionsField Description7CMP0CMP0 Clock Gate ControlThis bit controls the clock gate to the CMP0 module.0 Bus clock to the CMP0 module is disabled.1 Bus clock to the CMP0 module is enabled.6GDU_CMPGDU_CMP Clock Gate ControlThis bit controls the clock gate to the GDU_CMP module.0 Bus clock to the GDU_CMP module is disabled.1 Bus clock to the GDU_CMP module is enabled.5ADC1ADC1 Clock Gate ControlThis bit controls the clock gate to the ADC1 module.0 Bus clock to the ADC1 module is disabled.1 Bus clock to the ADC1 module is enabled.4ADC0ADC0 Clock Gate ControlThis bit controls the clock gate to the ADC0 module.0 Bus clock to the ADC0 module is disabled.1 Bus clock to the ADC0 module is enabled.3IRQIRQ Clock Gate ControlThis bit controls the clock gate to the IRQ module.0 Bus clock to the IRQ module is disabled.1 Bus clock to the IRQ module is enabled.2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1PDBPDB Clock Gate ControlThis bit controls the clock gate to the PDB module.Table continues on the next page...Memory map and register definitionMC9S08SU16 Reference Manual, Rev. 5, 4/2017118 NXP Semiconductors
