NXP Semiconductors KL25 Series Reference Manual Manual pdf 236 page image
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NXP Semiconductors KL25 Series Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Overview
  32. Typographic notation
  34. KL25 Sub-Family Introduction
  35. Module functional categories
  36. ARM® Cortex™-M0+ Core Modules
  37. Memories and Memory Interfaces
  38. Security and Integrity modules
  39. Communication interfaces
  40. Human-machine interfaces
  41. Introduction
  42. KL25 Sub-Family Reference Manual, Rev. 3, September
  43. Analog reference options
  44. Nested Vectored Interrupt Controller (NVIC) Configuration
  45. Asynchronous wake-up interrupt controller (AWIC) configuration
  46. System Modules
  47. System Mode Controller (SMC) Configuration
  48. Low-Leakage Wake-up Unit (LLWU) Configuration
  49. MCM Configuration
  50. Crossbar-Light Switch Configuration
  51. Peripheral Bridge Configuration
  52. DMA request multiplexer configuration
  53. DMA Controller Configuration
  54. Computer Operating Properly (COP) Watchdog Configuration
  55. Clock Modules
  56. OSC Configuration
  58. Flash Memory Controller Configuration
  60. Analog
  61. CMP Configuration
  62. bit DAC Configuration
  63. Timers
  64. PIT Configuration
  65. Low-power timer configuration
  66. RTC configuration
  68. SPI configuration
  69. I2C Configuration
  70. UART Configuration
  71. Human-machine interfaces (HMI)
  72. TSI Configuration
  73. Memory Map
  75. Flash Memory Map
  76. Alternate Non-Volatile IRC User Trim Description
  77. Peripheral bridge (AIPS-Lite) memory map
  80. Modules Restricted Access in User Mode
  82. Clock definitions
  83. Device clock summary
  84. Internal clocking requirements
  85. VLPR mode clocking
  86. Clock Gating
  87. PMC 1-kHz LPO clock
  88. RTC clocking
  89. TPM clocking
  90. UART clocking
  92. Power-on reset (POR)
  93. MCU Resets
  94. Reset Pin
  96. Boot sequence
  98. DMA Wakeup
  99. Compute Operation
  100. Peripheral Doze
  102. Entering and exiting power modes
  104. Security Interactions with Debug
  106. SWD status and control registers
  107. MDM-AP Control Register
  108. MDM-AP Status Register
  110. Micro Trace Buffer (MTB)
  112. Port control and interrupt module features
  114. KL25 Pinouts
  115. Module Signal Description Tables
  116. Core Modules
  122. Detailed signal description
  123. Pin Control Register n (PORTx_PCRn)
  124. Global Pin Control Low Register (PORTx_GPCLR)
  125. Global Pin Control High Register (PORTx_GPCHR)
  126. Functional description
  127. Global pin control
  129. System Options Register 1 (SIM_SOPT1)
  130. SOPT1 Configuration Register (SIM_SOPT1CFG)
  131. System Options Register 2 (SIM_SOPT2)
  132. System Options Register 4 (SIM_SOPT4)
  133. System Options Register 5 (SIM_SOPT5)
  134. System Options Register 7 (SIM_SOPT7)
  135. System Device Identification Register (SIM_SDID)
  136. System Clock Gating Control Register 4 (SIM_SCGC4)
  137. System Clock Gating Control Register 5 (SIM_SCGC5)
  138. System Clock Gating Control Register 6 (SIM_SCGC6)
  139. System Clock Gating Control Register 7 (SIM_SCGC7)
  140. System Clock Divider Register 1 (SIM_CLKDIV1)
  142. Flash Configuration Register 2 (SIM_FCFG2)
  143. Unique Identification Register Mid Low (SIM_UIDML)
  144. COP Control Register (SIM_COPC)
  145. Service COP Register (SIM_SRVCOP)
  147. Memory map and register descriptions
  148. Power Mode Control register (SMC_PMCTRL)
  149. Stop Control Register (SMC_STOPCTRL)
  150. Power Mode Status register (SMC_PMSTAT)
  152. Power mode entry/exit sequencing
  153. Run modes
  154. Wait modes
  155. Stop modes
  156. Debug in low power modes
  159. I/O retention
  160. Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)
  161. Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)
  162. Regulator Status And Control register (PMC_REGSC)
  164. Modes of operation
  165. Block diagram
  166. LLWU signal descriptions
  167. LLWU Pin Enable 1 register (LLWU_PE1)
  168. LLWU Pin Enable 2 register (LLWU_PE2)
  169. LLWU Pin Enable 3 register (LLWU_PE3)
  170. LLWU Pin Enable 4 register (LLWU_PE4)
  171. LLWU Module Enable register (LLWU_ME)
  172. LLWU Flag 1 register (LLWU_F1)
  173. LLWU Flag 2 register (LLWU_F2)
  174. LLWU Flag 3 register (LLWU_F3)
  175. LLWU Pin Filter 1 register (LLWU_FILT1)
  176. LLWU Pin Filter 2 register (LLWU_FILT2)
  178. LLS mode
  181. System Reset Status Register 1 (RCM_SRS1)
  182. Reset Pin Filter Control register (RCM_RPFC)
  183. Reset Pin Filter Width register (RCM_RPFW)
  187. Memory Map and Register Definition
  188. Additional Details on Decorated Addresses and GPIO Accesses
  189. Application Information
  191. Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  192. Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
  194. Compute Operation Control Register (MCM_CPO)
  196. Features
  199. MTB_DWT Memory Map
  202. Arbitration
  203. Initialization/application information
  205. General operation
  208. External signal description
  210. DMA channels with periodic triggering capability
  211. Freescale Semiconductor, Inc
  212. DMA channels with no triggering capability
  220. DMA Transfer Overview
  221. Memory Map and Registers
  222. Source Address Register (DMA_SARn)
  223. Destination Address Register (DMA_DARn)
  224. DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
  226. DMA Control Register (DMA_DCRn)
  232. Dual-Address Data Transfer Mode
  233. Advanced Data Transfer Controls: Auto-Alignment
  234. Termination
  241. MCG Control 1 Register (MCG_C1)
  242. MCG Control 2 Register (MCG_C2)
  243. MCG Control 3 Register (MCG_C3)
  245. MCG Control 5 Register (MCG_C5)
  246. MCG Control 6 Register (MCG_C6)
  247. MCG Status Register (MCG_S)
  249. MCG Status and Control Register (MCG_SC)
  250. MCG Auto Trim Compare Value High Register (MCG_ATCVH)
  251. MCG Control 7 Register (MCG_C7)
  252. MCG Control 9 Register (MCG_C9)
  257. Low Power Bit Usage
  259. MCG PLL clock
  260. Initialization / Application information
  263. Using a 32.768 kHz reference
  276. External Crystal / Resonator Connections
  277. External Clock Connections
  278. Memory Map/Register Definitions
  281. OSC Module Modes
  282. Counter
  283. Reset
  290. Glossary
  292. Flash Configuration Field Description
  293. Register Descriptions
  302. Flash Protection
  303. Flash Operation in Low-Power Modes
  304. Flash Reads and Ignored Writes
  309. Margin Read Commands
  310. Flash Command Description
  323. Security
  325. Reset Sequence
  328. ADC Signal Descriptions
  329. Voltage Reference Select
  330. Analog Channel Inputs (ADx)
  331. ADC Status and Control Registers 1 (ADCx_SC1n)
  334. ADC Configuration Register 1 (ADCx_CFG1)
  336. ADC Configuration Register 2 (ADCx_CFG2)
  337. ADC Data Result Register (ADCx_Rn)
  338. Compare Value Registers (ADCx_CVn)
  339. Status and Control Register 2 (ADCx_SC2)
  341. Status and Control Register 3 (ADCx_SC3)
  343. ADC Offset Correction Register (ADCx_OFS)
  344. ADC Minus-Side Gain Register (ADCx_MG)
  345. ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
  347. ADC Plus-Side General Calibration Value Register (ADCx_CLP1)
  348. ADC Minus-Side General Calibration Value Register (ADCx_CLMD)
  349. ADC Minus-Side General Calibration Value Register (ADCx_CLM4)
  350. ADC Minus-Side General Calibration Value Register (ADCx_CLM2)
  351. ADC Minus-Side General Calibration Value Register (ADCx_CLM0)
  352. Clock select and divide control
  353. Voltage reference selection
  354. Conversion control
  362. Automatic compare function
  363. Calibration function
  365. User-defined offset function
  366. Temperature sensor
  367. MCU Normal Stop mode operation
  368. MCU Low-Power Stop mode operation
  372. Sources of error
  379. bit DAC key features
  380. ANMUX key features
  381. CMP block diagram
  384. CMP Control Register 1 (CMPx_CR1)
  386. CMP Filter Period Register (CMPx_FPR)
  387. DAC Control Register (CMPx_DACCR)
  388. MUX Control Register (CMPx_MUXCR)
  398. Power modes
  399. Startup and operation
  400. Low-pass filter
  402. CMP interrupts
  403. CMP Asyncrhonous DMA support
  405. DAC interrupts
  408. Memory map/register definition
  409. DAC Data High Register (DACx_DATnH)
  410. DAC Control Register (DACx_C0)
  411. DAC Control Register 1 (DACx_C1)
  413. DMA operation
  419. TPM_EXTCLK — TPM External Clock
  421. Status and Control (TPMx_SC)
  422. Counter (TPMx_CNT)
  423. Modulo (TPMx_MOD)
  424. Channel (n) Status and Control (TPMx_CnSC)
  426. Channel (n) Value (TPMx_CnV)
  428. Configuration (TPMx_CONF)
  431. Prescaler
  433. Input Capture Mode
  434. Output Compare Mode
  436. Edge-Aligned PWM (EPWM) Mode
  437. Center-Aligned PWM (CPWM) Mode
  439. Registers Updated from Write Buffers
  440. Reset Overview
  446. PIT Upper Lifetime Timer Register (PIT_LTMR64H)
  447. Timer Load Value Register (PIT_LDVALn)
  448. Timer Control Register (PIT_TCTRLn)
  449. Timer Flag Register (PIT_TFLGn)
  451. Interrupts
  452. Example configuration for chained timers
  453. Example configuration for the lifetime timer
  457. LPTMR signal descriptions
  458. Low Power Timer Control Status Register (LPTMRx_CSR)
  459. Low Power Timer Prescale Register (LPTMRx_PSR)
  461. Low Power Timer Compare Register (LPTMRx_CMR)
  464. LPTMR compare
  465. LPTMR hardware trigger
  467. RTC Signal Descriptions
  468. RTC Time Seconds Register (RTC_TSR)
  469. RTC Time Alarm Register (RTC_TAR)
  470. RTC Control Register (RTC_CR)
  472. RTC Status Register (RTC_SR)
  473. RTC Lock Register (RTC_LR)
  474. RTC Interrupt Enable Register (RTC_IER)
  476. Time counter
  477. Time alarm
  478. Update mode
  481. USB On-The-Go
  482. USB-FS Features
  483. Programmers interface
  484. RX vs. TX as a USB target device or USB host
  485. Addressing BDT entries
  488. USB transaction
  492. Peripheral ID register (USBx_PERID)
  493. Peripheral ID Complement register (USBx_IDCOMP)
  494. Peripheral Additional Info register (USBx_ADDINFO)
  495. OTG Interrupt Control Register (USBx_OTGICR)
  496. OTG Status register (USBx_OTGSTAT)
  497. OTG Control register (USBx_OTGCTL)
  498. Interrupt Status register (USBx_ISTAT)
  499. Interrupt Enable register (USBx_INTEN)
  500. Error Interrupt Status register (USBx_ERRSTAT)
  501. Error Interrupt Enable register (USBx_ERREN)
  503. Control register (USBx_CTL)
  504. Address register (USBx_ADDR)
  505. BDT Page Register 1 (USBx_BDTPAGE1)
  506. Frame Number Register High (USBx_FRMNUMH)
  507. SOF Threshold Register (USBx_SOFTHLD)
  508. BDT Page Register 2 (USBx_BDTPAGE2)
  509. USB Control register (USBx_USBCTRL)
  510. USB OTG Observe register (USBx_OBSERVE)
  511. USB OTG Control register (USBx_CONTROL)
  512. Frame Adjust Register (USBx_USBFRMADJUST)
  513. OTG and Host mode operation
  516. On-The-Go operation
  517. OTG dual role A device operation
  518. OTG dual role B device operation
  526. Block Diagrams
  529. SPSCK — SPI Serial Clock
  532. SPI control register 2 (SPIx_C2)
  533. SPI baud rate register (SPIx_BR)
  534. SPI status register (SPIx_S)
  536. SPI data register (SPIx_D)
  537. SPI match register (SPIx_M)
  538. Master Mode
  539. Slave Mode
  540. SPI Transmission by DMA
  542. SPI Clock Formats
  545. SPI Baud Rate Generation
  546. Special Features
  548. Error Conditions
  553. Pseudo-Code Example
  559. I2C Address Register 1 (I2Cx_A1)
  560. I2C Frequency Divider register (I2Cx_F)
  561. I2C Control Register 1 (I2Cx_C1)
  563. I2C Status register (I2Cx_S)
  564. I2C Data I/O register (I2Cx_D)
  565. I2C Control Register 2 (I2Cx_C2)
  566. I2C Programmable Input Glitch Filter register (I2Cx_FLT)
  567. I2C Range Address register (I2Cx_RA)
  568. I2C SMBus Control and Status register (I2Cx_SMB)
  570. I2C Address Register 2 (I2Cx_A2)
  576. bit address
  578. Address matching
  581. Resets
  583. Programmable input glitch filter
  584. Address matching wakeup
  585. DMA support
  593. Register definition
  594. UART Baud Rate Register High (UARTx_BDH)
  595. UART Baud Rate Register Low (UARTx_BDL)
  597. UART Control Register 2 (UARTx_C2)
  598. UART Status Register 1 (UARTx_S1)
  600. UART Status Register 2 (UARTx_S2)
  602. UART Control Register 3 (UARTx_C3)
  603. UART Data Register (UARTx_D)
  604. UART Match Address Registers 1 (UARTx_MA1)
  605. UART Match Address Registers 2 (UARTx_MA2)
  606. UART Control Register 5 (UARTx_C5)
  609. Receiver functional description
  612. Additional UART functions
  614. Interrupts and status flags
  620. UART Baud Rate Register: High (UARTx_BDH)
  621. UART Control Register 1 (UARTx_C1)
  631. Baud rate generation
  644. Port Data Output Register (GPIOx_PDOR)
  645. Port Set Output Register (GPIOx_PSOR)
  646. Port Toggle Output Register (GPIOx_PTOR)
  647. Port Data Direction Register (GPIOx_PDDR)
  649. Port Data Output Register (FGPIOx_PDOR)
  650. Port Set Output Register (FGPIOx_PSOR)
  651. Port Toggle Output Register (FGPIOx_PTOR)
  652. Port Data Direction Register (FGPIOx_PDDR)
  653. IOPORT
  661. TSI DATA Register (TSIx_DATA)
  662. TSI Threshold Register (TSIx_TSHD)
  663. Capacitance measurement
  666. TSI measurement result
  667. Scan times
  668. Current source
  669. Wake up MCU from low power modes
NXP Semiconductors KL25 Series Reference Manual Manual pdf 236 page image
The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge(VLLDBGACK) bit that is set to release the ARM core being held in reset following aVLLS recovery. The debugger reinitializes all debug IP, and then asserts theVLLDBGACK control bit to allow the RCM to release the ARM core from reset andallow CPU operation to begin.The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clearsautomatically due to the reset generated as part of the next VLLS recovery.Functional descriptionKL25 Sub-Family Reference Manual, Rev. 3, September 2012236 Freescale Semiconductor, Inc.
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This manual is suitable for:
KL25 SeriesMKL25Z128VFM4MKL25Z128VFT4MKL25Z128VLH4MKL25Z128VLK4MKL25Z32VFM4MKL25Z32VFT4MKL25Z32VLH4MKL25Z32VLK4MKL25Z64VFM4MKL25Z64VFT4MKL25Z64VLH4MKL25Z64VLK4
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