The CMP does not support window compare function and CMP_CR1[WE] must alwaysbe written to 0. The sample function has limited functionality since the SAMPLE input tothe block is not connected to a valid input. Usage of sample operation is limited to adivided version of the bus clock (CMP_CR1[SE] = 0).Due to the pin number limitation, the CMP pass through mode is not supported by thisdevice, so the CMPx_MUXCR[PSTM] must be left as 0.3.7.2.2 CMP input connectionsThe following table shows the fixed internal connections to the CMP.Table 3-34. CMP input connectionsCMP Inputs CMP0IN0 CMP0_IN0IN1 CMP0_IN1IN2 CMP0_IN2IN3 CMP0_IN3IN4 12-bit DAC0 reference/ CMP0_IN4IN5 CMP0_IN5IN6 Bandgap1IN7 6-bit DAC0 reference1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer bysetting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification.3.7.2.3 CMP external referencesThe 6-bit DAC sub-block supports selection of two references. For this device, thereferences are connected as follows:• VREFH - Vin1 input. When using VREFH, any ADC conversion using this samereference at the same time is negatively impacted.• VDD - Vin2 input3.7.2.4 CMP trigger modeThe CMP and 6-bit DAC sub-block supports trigger mode operation when theCMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate acompare sequence that must first enable the CMP and DAC prior to performing a CMPoperation and capturing the output. In this device, control for this two staged sequencingAnalogKL25 Sub-Family Reference Manual, Rev. 3, September 201282 Freescale Semiconductor, Inc.
