Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0ACOMP1ACOMP0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MTBDWT_TBCTRL field descriptionsField Description31–28NUMCOMPNumber of ComparatorsThis read-only field specifies the number of comparators in the MTB_DWT. This implementation includestwo registers.27–2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1ACOMP1Action based on Comparator 1 matchWhen the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare hastriggered and the trace buffer's recording state is changed.0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].0ACOMP0Action based on Comparator 0 matchWhen the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address compare hastriggered and the trace buffer's recording state is changed. The assertion of MTBDWT_FCT0[MATCHED]is caused by the following conditions:• Address match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0• Data match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0}• Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 whenMTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1}0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].Memory Map and Register DefinitionKL25 Sub-Family Reference Manual, Rev. 3, September 2012324 Freescale Semiconductor, Inc.
