PORTx_PCRn field descriptions (continued)Field Description23–20ReservedThis field is reserved.This read-only field is reserved and always has the value 0.19–16IRQCInterrupt ConfigurationThis field is read only for pins that do not support interrupt generation.The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configuredto generate interrupt/DMA request as follows:0000 Interrupt/DMA request disabled.0001 DMA request on rising edge.0010 DMA request on falling edge.0011 DMA request on either edge.1000 Interrupt when logic zero.1001 Interrupt on rising edge.1010 Interrupt on falling edge.1011 Interrupt on either edge.1100 Interrupt when logic one.Others Reserved.15–11ReservedThis field is reserved.This read-only field is reserved and always has the value 0.10–8MUXPin Mux ControlNot all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result inconfiguring the pin for a different pin muxing slot.The corresponding pin is configured in the following pin muxing slot as follows:000 Pin disabled (analog).001 Alternative 1 (GPIO).010 Alternative 2 (chip-specific).011 Alternative 3 (chip-specific).100 Alternative 4 (chip-specific).101 Alternative 5 (chip-specific).110 Alternative 6 (chip-specific).111 Alternative 7 (chip-specific).7ReservedThis field is reserved.This read-only field is reserved and always has the value 0.6DSEDrive Strength EnableThis bit is read only for pins that do not support a configurable drive strength.Drive strength configuration is valid in all digital pin muxing modes.0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output.5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4PFEPassive Filter EnableThis bit is read only for pins that do not support a configurable passive input filter.Passive filter configuration is valid in all digital pin muxing modes.Table continues on the next page...Memory map and register definitionKL25 Sub-Family Reference Manual, Rev. 3, September 2012184 Freescale Semiconductor, Inc.
