1 2 3 4next5..v_wxyznextnext400v_wxyz nextnext5..v_wxyz rdatanextrdataubfxCYCLE RULERhclkBME AHB Input Busmx_haddrmx_hattrmx_hwritemx_hwdatamx_hrdatamx_hreadyBME AHB Output Bussx_haddrsx_hattrsx_hwritesx_hwdatasx_hrdatasx_hreadyBME States + Datapathcontrol_state_dp1control_state_dp2reg_addr_data_dpFigure 17-8. Decorated load: unsigned bit field insert timing diagramThe decorated unsigned bit field extract follows the same execution template shown inthe above figure, a 2-cycle read operation:• Cycle x, 1st AHB address phase: Read from input bus is translated into a readoperation on the output bus with the actual memory address (with the decorationremoved) and then captured in a register• Cycle x+1, 2nd AHB address phase: Idle cycle• Cycle x+1, 1st AHB data phase: A bit mask is generated based on the starting bitposition and the field width; the mask is AND'ed with the memory read data toisolate the bit field; the resulting data is captured in a data register; the input buscycle is stalled• Cycle x+2, 2nd AHB data phase: Registered data is logically right shifted for properalignment and driven onto the input read data busNOTEAny wait states inserted by the peripheral slave device(sx_hready = 0) are simply passed through the BME back to themaster input bus, stalling the AHB transaction cycle for cycle.Chapter 17 Bit Manipulation Engine (BME)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 283
