Table 3-5. Reference links to related information (continued)Topic Related module ReferenceSystem memory map System memory mapClocking Clock distributionPower management Power managementPrivate Peripheral Bus(PPB)ARM Cortex-M0+ core ARM Cortex-M0+ core3.3.2.1 Interrupt priority levelsThis device supports 4 priority levels for interrupts. Therefore, in the NVIC each sourcein the IPR registers contains 2 bits. For example, IPR0 is shown below:31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R IRQ3 0 0 0 0 0 0 IRQ2 0 0 0 0 0 0 IRQ1 0 0 0 0 0 0 IRQ0 0 0 0 0 0 0W3.3.2.2 Non-maskable interruptThe non-maskable interrupt request to the NVIC is controlled by the external NMI signal.The pin the NMI signal is multiplexed on, must be configured for the NMI function togenerate the non-maskable interrupt request.3.3.2.3 Interrupt channel assignmentsThe interrupt vector assignments are defined in the following table.• Vector number — the value stored on the stack when an interrupt is serviced.• IRQ number — non-core interrupt source count, which is the vector number minus16.The IRQ number is used within ARM's NVIC documentation.Table 3-7. Interrupt vector assignmentsAddress Vector IRQ1 NVICIPRregisternumber2Source module Source descriptionARM Core System Handler VectorsTable continues on the next page...Core ModulesKL25 Sub-Family Reference Manual, Rev. 3, September 201252 Freescale Semiconductor, Inc.
