IndexMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Index-4 Freescale SemiconductorPin descriptions, ??–19-38address bus, 19-19byte strobes, 19-20clock, 19-25data bus, 19-19dynamic data bus sizing, 19-19general-purpose I/O ports, 19-24interrupt request inputs, 19-23JTAG test access port and BDM debug port, 19-35–19-37operating mode configuration, 19-37PLI TDM ports, 19-30–19-35power supply, 19-38QSPI signals, 19-29–??RSTI, 19-23SDRAMbank selects, 19-23clock enable, 19-22column address strobe, 19-22row address 10, 19-23row address strobe, 19-22write enable, 19-22UART0 module signals, 19-24–19-25USB module signals and PA, 19-25–19-27Pipelinesinstruction fetch, 2-2operand execution, 2-2PLICaperiodic status register, 13-23application examples, 13-35–13-42automatic echo mode, 13-9B1 datareceive registers, 13-15transmit registers, 13-17B2 datareceive registers, 13-16transmit registers, 13-17B-ChannelHDLC encoded data, 13-6unencoded data, 13-5clock select register, 13-34clock synthesis, 13-11D datareceive registers, 13-16transmit registers, 13-18D-ChannelHDLC encoded data, 13-6unencoded data, 13-7D-Channel request register, 13-32D-Channel status register, 13-31frame sync synthesis, 13-13GCI C/I channelreceive registers, 13-28transmit registers, 13-29transmit status register, 13-30GCI interrupts aperiodic status, 13-10GCI monitor channelreceive registers, 13-24transmit abort register, 13-26transmit registers, 13-25transmit status register, 13-27GCI/IDLB- and D-Channelreceive data registers, 13-3transmit data registers, 13-4B- and D-Channel bit alignment, 13-5block, 13-3D-Channel contention, 13-8looping modes, 13-8periodic frame interrupts, 13-9initialization, 13-35interrupt configurationexample, 13-37registers, 13-20interrupt control, 13-11introduction, 13-1local loopback mode, 13-9loopback control register, 13-20periodic status registers, 13-22port configurationexample, 13-35registers, 13-18register memory map, 13-13registers, general, 13-15remote loopback mode, 13-9super frame sync generation, 13-13sync delay registers, 13-33timing generator, 13-11Portsparallel input/output, 1-6Power management registers, 6-7Program counter, 2-6Programming modelPWM, 18-2QSPI, 14-9Programming modelsEthernet, 11-10instruction cache, 4-12MAC, 2-7overview, 2-4ROM, 4-5SIM, 6-2SRAM, 4-2supervisor, 2-7, 2-7user, 2-4PST outputs, 5-3PULSE instruction, 5-3PWMcontrol register, 18-3operation, 18-2overview, 18-1
