IndexMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor Index-5programming model, 18-2width register, 18-4QQSPIaddress register, 14-14baud rate selection, 14-6command RAM bit description, 14-15data register, 14-14delay register, 14-11interrupt, 14-13mode register, 14-9module description, 14-1operation, 14-3overview and features, 14-1programmingexample, 14-16model, 14-9RAMcommand, 14-6model, 14-4receive, 14-5transmit, 14-6slave bus interface, 14-3transferdata, 14-8delays, 14-7length, 14-8wrap register, 14-12RRAMQSPI command bit description, 14-15USB configuration, 12-28, 12-30RAM base address registers, 2-9RAMBARoverview, 4-3power management programming, 4-4Read/write, bus, 20-2RegistersA0–A6, 2-5A7, 2-5AATR, 5-7ABLR/ABHR, 5-6, 5-9access control, 2-9, 4-14activate low-power, 6-10address, 2-5address (A0 – A6), 2-5ALPR, 6-10B2 data transmit, 13-17BI data receive, 13-15cache configuration, 2-9cache control, 4-12CACR, 2-9CCR, 2-6chip selectbase, 8-3general, 8-2option, 8-5condition code, 2-6, 2-6condition code (CCR), 2-6CSBR, 8-3CSOR, 8-5CSR, 5-10D data receive, 13-16D0–D7, 2-5data, 2-5data breakpoint/mask, 5-12data D0 - D7, 2-5DBCR, 10-6D-Channel request, 13-32DDAR, 10-6debug attribute trigger, 5-7descriptor active, 11-15device identification, 6-11DIR, 10-4DMAbyte count, 10-6controller, 10-2destination address, 10-6interrupt, 10-4mode, 10-2sourse address, 10-5DMR, 10-2DSAR, 10-5Ethernet control, 11-11FIFOreceive bound, 11-19receive start, 11-20transmit start, 11-22GCIC/I channel transmit status, 13-30monitor channel transmit abort, 13-26GPIOcontrol port, 17-2–17-8data, 17-11data direction, 17-10hash tablehigh, 11-28low, 11-29IDCODE, 6-11integer data formats in, 2-10interruptevent, 11-12mask, 11-13vector status, 11-14interrupt controllerpending and mask, 7-5, 7-5
