NXP Semiconductors MCF5272 ColdFire User Manual Manual pdf 474 page image
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NXP Semiconductors MCF5272 ColdFire User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. MCF5272 ColdFire ® Integrated Microprocessor User's Manual,
  36. Overview
  37. general information
  38. acronyms and abbreviations
  39. MCF5272 Key Features
  40. MCF5272 Block Diagram
  41. MCF5272 Architecture
  42. System Integration Module (SIM)
  43. Power Management
  44. Timer Module
  45. Pulse-Width Modulation (PWM) Unit
  46. Features and Enhancements
  47. ColdFire Pipeline
  48. ColdFire Multiply-Accumulate Functionality Diagram
  49. Hardware Divide Unit
  50. ColdFire Programming Model
  51. Condition Code Register (CCR)
  52. MAC Programming Model
  53. Status Register (SR)
  54. Cache Control Register (CACR)
  55. Organization of Integer Data Formats in Data Registers
  56. Memory Operand Addressing
  57. Addressing Mode Summary
  58. Instruction Set Summary
  60. Supervisor-Mode Instruction Set Summary
  61. Instruction Timing
  62. MOVE Instruction Execution Times
  63. Move Long Execution Times
  64. Execution Timings—One-Operand Instructions
  65. Miscellaneous Instruction Execution Times
  66. Branch Instruction Execution Times
  67. Exception Vector Assignments
  68. Exception Stack Frame Form
  69. Processor Exceptions
  70. ColdFire MAC Multiplication and Accumulation
  72. General Operation
  73. MAC Instruction Set Summary
  74. Local Memory
  75. Local Memory Registers
  76. SRAM Base Address Register (RAMBAR)
  77. SRAM Initialization
  78. ROM Base Address Register (ROMBAR)
  79. Programming ROMBAR for Power Management
  80. Instruction Cache Overview
  81. Instruction Cache Block Diagram
  82. Caching Modes
  83. Reset
  84. Instruction Cache Operation as Defined by CACR[CENB,CEIB]
  86. CACR Field Descriptions
  87. Access Control Register Format (ACRn)
  88. Processor/Debug Module Interface
  89. PSTCLK Timing
  90. Real-Time Trace Support
  91. Begin Execution of Taken Branch (PST = 0x5)
  92. Example JMP Instruction Output on PST/DDATA
  93. Debug Programming Model
  94. Address Attribute Trigger Register (AATR)
  95. Address Breakpoint Registers (ABLR, ABHR)
  96. Configuration/Status Register (CSR)
  97. Data Breakpoint/Mask Registers (DBR and DBMR)
  98. Program Counter Breakpoint Register (PBR)
  99. Trigger Definition Register (TDR)
  100. Background Debug Mode (BDM)
  101. CPU Halt
  102. BDM Serial Interface Timing
  103. Receive BDM Packet
  104. BDM Command Set
  105. BDM Command Format
  106. Command Sequence Diagram
  107. Command Set Descriptions
  108. WAREG / WDREG Command Format
  109. Read Memory Location ( READ )
  110. WRITE Command Format
  111. WRITE Command Sequence
  112. NOP Command Format
  113. Definition of DRc Encoding—Read
  114. WDMREG BDM Command Format
  115. Theory of Operation
  116. Emulator Mode
  117. Processor Status, DDATA Definition
  118. PST/DDATA Specification for User-Mode Instructions
  119. Supervisor Instruction Set
  120. Recommended BDM Connector
  121. SIM Block Diagram
  122. Programming Model
  123. Module Base Address Register (MBAR)
  125. System Configuration Register (SCR)
  126. System Protection Register (SPR)
  127. Power Management Register (PMR)
  129. USB and USART Power Down Modes
  130. Activate Low-Power Register (ALPR)
  131. Device Identification Register (DIR)
  132. Watchdog Reset Reference Register (WRRR)
  133. Watchdog Counter Register (WCR)
  135. Interrupt Controller Block Diagram
  136. ColdFire Core
  137. Interrupt Control Register 1 (ICR1)
  138. Interrupt Control Register 2 (ICR2)
  139. Interrupt Source Register (ISR)
  140. Programmable Interrupt Transition Register (PITR)
  141. Programmable Interrupt Wakeup Register (PIWR)
  142. Programmable Interrupt Vector Register (PIVR)
  143. MCF5272 Interrupt Vector Table
  145. Boot CS0 Operation
  146. Chip Select Base Registers (CSBRn)
  147. Output Read/Write Strobe Levels versus Chip Select EBI Code
  148. Chip Select Option Registers (CSORn)
  150. SDRAM Controller Signals
  151. Pin TSOP SDRAM Pin Definition
  152. Interface to SDRAM Devices
  153. Internal Address Multiplexing (16-Bit Data Bus)
  154. SDRAM Configuration Register (SDCR)
  155. SDCR Field Descriptions
  156. SDRAM Timing Register (SDTR)
  157. Auto Initialization
  158. Performance
  159. SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port
  160. Example Setup Time Violation on SDRAM Data Input during Write
  161. Timing Refinement with Inverted SDCLK
  162. Timing Refinement with Effective CAS Latency
  163. SDRAM Read Accesses
  164. SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1
  165. SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1
  166. SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1
  167. SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1
  168. SDRAM Refresh Cycle
  169. Enter SDRAM Self-Refresh Mode
  170. Exit SDRAM Self-Refresh Mode
  171. DMA Data Transfer Types
  172. DMA Mode Register (DMR)
  173. DMA Interrupt Register (DIR)
  174. DMA Source Address Register (DSAR)
  175. DMA Destination Address Register (DDAR)
  177. Ethernet Block Diagram
  178. Transceiver Connection
  179. Ethernet Frame Format
  180. FEC Frame Reception
  181. CAM Interface
  182. Ethernet Address Recognition Flowchart
  183. Hash Table Algorithm
  184. Ethernet Error-Handling Procedure
  186. Ethernet Control Register (ECR)
  187. Interrupt Event Register (EIR)
  188. Interrupt Mask Register (EIMR)
  189. Interrupt Vector Status Register (IVSR)
  190. Receive Descriptor Active Register (RDAR)
  191. Transmit Descriptor Active Register (TDAR)
  192. MII Management Frame Register (MMFR)
  193. MII Speed Control Register (MSCR)
  194. FIFO Receive Bound Register (FRBR)
  195. FIFO Receive Start Register (FRSR)
  196. Transmit FIFO Watermark (TFWR)
  197. FIFO Transmit Start Register (TFSR)
  198. Receive Control Register (RCR)
  199. Maximum Frame Length Register (MFLR)
  200. Transmit Control Register (TCR)
  201. RAM Perfect Match Address Low (MALR)
  202. RAM Perfect Match Address High (MAUR)
  203. Hash Table High (HTUR)
  204. Hash Table Low (HTLR)
  205. Pointer-to-Receive Descriptor Ring (ERDSR)
  206. Pointer-to-Transmit Descriptor Ring (ETDSR)
  207. Receive Buffer Size (EMRBR)
  208. Initialization Sequence
  209. FEC Initialization
  210. Receive Buffer Descriptor (RxBD)
  211. RxBD Field Descriptions
  212. Transmit Buffer Descriptor (TxBD)
  213. Differences between MCF5272 FEC and MPC860T FEC
  214. Introduction
  215. The USB "Tiered Star" Topology
  216. USB Module Block Diagram
  217. Clock Generator
  218. Endpoint Controllers
  219. Register Description and Programming Model
  220. USB Frame Number Register (FNR)
  221. USB Real-Time Frame Monitor Register (RFMR)
  222. USB Real-Time Frame Monitor Match Register (RFMMR)
  223. USB Alternate Settings Register (ASR)
  224. USB Device Request Data 1 Register (DRR1)
  225. USB Specification Number Register (SPECR)
  226. USB Endpoint 0 IN Configuration Register (IEP0CFG)
  227. USB Endpoint 0 OUT Configuration Register
  228. USB Endpoint 0 Control Register (EP0CTL)
  229. USB Endpoint 1-7 Control Register (EPnCTL)
  230. USB Endpoint 0 Interrupt Mask (EP0IMR and General/Endpoint 0 Interrupt Registers (EP0ISR)
  231. USB Endpoints 1–7 Interrupt Status Registers (EPnISR)
  232. USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR)
  233. USB Endpoint 0-7 Data Registers (EPnDR)
  234. USB Endpoint 0-7 Data Present Registers (EPnDPR)
  235. Example USB Configuration Descriptor Structure
  236. USB Module Access Times
  237. Software Architecture and Application Notes
  238. FIFO Configuration
  239. Control, Bulk, and Interrupt Endpoints
  240. IN Endpoints
  241. Endpoint Halt Feature
  242. Recommended USB Line Interface
  243. USB Protection Circuit
  245. PLIC System Diagram
  246. GCI/IDL Receive Data Flow
  247. GCI/IDL B-Channel Receive Data Register Demultiplexing
  248. GCI/IDL B Data Transmit Register Multiplexing
  249. B-Channel Unencoded and HDLC Encoded Data
  250. D-Channel HDLC Encoded and Unencoded Data
  251. D-Channel Contention
  252. GCI/IDL Loopback Mode
  253. Periodic Frame Interrupt
  254. Interrupt Control
  255. PLIC Internal Timing Signal Routing
  256. Super Frame Sync Generation
  257. B1 Receive Data Registers P0B1RR–P3B1RR
  258. B2 Receive Data Registers P0B2RR – P3B2RR
  259. B1 Transmit Data Registers P0B1TR–P3B1TR
  260. D Transmit Data Registers P0DTR–P3DTR
  261. P0CR–P3CR Field Descriptions
  262. Loopback Control Register (PLCR)
  263. P0ICR–P3ICR Field Descriptions
  264. Periodic Status Registers (P0PSR–P3PSR)
  265. Aperiodic Status Register (PASR)
  266. GCI Monitor Channel Receive Registers (P0GMR–P3GMR)
  267. GCI Monitor Channel Transmit Registers (P0GMT–P3GMT)
  268. GCI Monitor Channel Transmit Abort Register (PGMTA)
  269. GCI Monitor Channel Transmit Status Register (PGMTS)
  270. GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
  271. GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
  272. GCI C/I Channel Transmit Status Register (PGCITSR)
  273. D-Channel Status Register (PDCSR)
  274. D-Channel Request Registers (PDRQR)
  275. Sync Delay Registers (P0SDR–P3SDR)
  276. Clock Select Register (PCSR)
  277. Application Examples
  278. Port 1 Configuration Register (P1CR)
  279. Port 1 Interrupt Configuration Register (P1ICR)
  280. ISDN SOHO PABX Example
  281. Standard IDL2 10-Bit Mode
  284. Standard IDL2 8-Bit Mode
  286. QSPI Block Diagram
  287. Interface and Pins
  288. QSPI RAM
  289. QSPI RAM Model
  290. Transmit RAM
  291. Transfer Delays
  292. Transfer Length
  293. QSPI Mode Register (QMR)
  294. QSPI Clocking and Data Transfer Example
  295. SPI Modes Timing
  296. QSPI Wrap Register (QWR)
  297. QSPI Interrupt Register (QIR)
  298. QSPI Address Register
  299. Command RAM Registers (QCR0–QCR15)
  300. Programming Example
  302. Timer Block Diagram
  303. Timer Mode Registers (TMR0–TMR3)
  304. Timer Reference Registers (TRR0–TRR3)
  305. Timer Event Registers (TER0–TER3)
  306. System Integration Module (SIM
  307. Serial Module Overview
  308. UART Module Programming Model
  309. UART Mode Registers 1 (UMR1n)
  310. UMR1n Field Descriptions
  311. UART Mode Register 2 (UMR2n)
  312. UART Status Registers (USRn)
  313. UART Clock-Select Registers (UCSRn)
  314. UART Command Registers (UCRn)
  315. UART Receiver Buffer (URBn)
  316. UART Transmitter Buffers (UTBn)
  317. UART Auxiliary Control Registers (UACRn)
  318. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
  319. UART Divider Upper Registers (UDUn)
  320. UART Transmitter FIFO Registers (UTFn)
  321. UART Receiver FIFO Registers (URFn)
  322. UART Fractional Precision Divider Control Registers (UFPDn)
  323. Interrupt Controller
  324. UART/RS-232 Interface
  325. Clocking Source Diagram
  326. External Clock
  327. Transmitter and Receiver Functional Diagram
  328. Transmitter Timing
  329. Receiver Timing
  330. Transmitter FIFO
  331. Looping Modes
  332. Automatic Echo
  333. Remote Loop-Back
  334. Multidrop Mode Timing Diagram
  335. UART Mode Programming Flowchart (Sheet 1 of 5)
  337. Port Control Registers
  338. Port A Control Register (PACNT)
  339. Port B Control Register (PBCNT)
  340. PBCNT Field Descriptions
  341. Port B Control Register Function Bits
  342. Port D Control Register (PDCNT)
  343. Port D Control Register Function Bits
  344. Port A Data Direction Register (PADDR)
  345. Port C Data Direction Register (PCDDR)
  346. PWM Block Diagram (3 Identical Modules)
  347. PWM Operation
  348. PWM Control Registers (PWCRn)
  349. PWM Width Register (PWWDn)
  350. MCF5272 Block Diagram with Signal Interfaces
  352. Signal List
  353. Signal Name and Description by Pin Number
  354. SDRAM Controller
  355. Bus Control Signals
  356. Read/Write (R/W)
  357. Transfer Acknowledge (TA/PB5)
  358. SDRAM Bank Selects (SDBA[1:0])
  359. General-Purpose I/O (GPIO) Ports
  360. Receive Serial Data Input (URT0_RxD/PB1)
  361. USB Transmit Data Negative (USB_TN/PA3)
  362. Ethernet Module
  363. Transmit Data (E_TxD0)
  364. Receive Error (E_RxER/PB14)
  365. QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL)
  366. Physical Layer Interface Controller TDM Ports and UART 1
  367. UART1 CTS (URT1_CTS/QSPI_CS2)
  368. GCI/IDL Data Out (DOUT1)
  369. GCI/IDL TDM Ports 2 and 3
  370. INT4 and Port 3 GCI/IDL Data In (INT4/DIN3)
  371. Test and Debug Data Out (TDO/DSO)
  372. Debug Data (DDATA[3:0])
  373. Power Supply Pins
  374. Features
  375. Address Bus (A[22:0])
  376. Transfer Error Acknowledge (TEA)
  377. Data Transfer Mechanism
  378. Internal Operand Representation
  379. Byte Strobe Operation for 32-Bit Data Bus
  380. External Bus Interface Types
  381. Longword Read; EBI = 00; 32-Bit Port; Internal Termination
  382. Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination
  383. Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination
  384. Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination
  385. Longword Read; EBI=11; 32-Bit Port; Internal Termination
  386. Word Write; EBI=11; 16/32-Bit Port; Internal Termination
  387. Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination
  388. Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination
  389. Burst Data Transfers
  390. Example of a Misaligned Longword Transfer
  391. Interrupt Cycles
  392. Longword Write Access To 32-Bit Port Terminated with TEA Timing
  393. Bus Arbitration
  394. Master Reset Timing
  395. Normal Reset Timing
  396. Software Watchdog Timer Reset Timing
  397. Soft Reset Timing
  399. Test Access Port Block Diagram
  400. TAP Controller State Machine
  401. Output Cell (O.Cell) (BC–1)
  402. Input Cell (I.Cell). Observe only (BC–4)
  403. Bidirectional Cell (IO.Cell) (BC–6)
  404. Instruction Register
  405. Bypass Register
  406. MCF5272 Pinout (196 MAPBGA)
  407. MAPBGA Package Dimensions (Case No. 1128A-01)
  408. Maximum Ratings
  409. Operating Temperature
  410. DC Electrical Specifications
  411. Clock Input Timing Diagram
  412. Processor Bus Input Timing Specifications
  413. General Input Timing Requirements
  414. Processor Bus Output Timing Specifications
  415. Read/Write SRAM Bus Timing
  416. SRAM Bus Cycle Terminated by TA
  417. SRAM Bus Cycle Terminated by TEA
  418. Reset and Mode Select/HIZ Configuration Timing
  419. Real-Time Trace AC Timing
  420. SDRAM Interface Timing Specifications
  421. SDRAM Signal Timing
  422. SDRAM Self-Refresh Cycle Timing
  423. MII Receive Signal Timing Diagram
  424. MII Transmit Signal Timing Diagram
  425. MII Async Inputs Timing Diagram
  426. MII Serial Management Channel Timing Diagram
  427. Timer Timing
  428. UART Timing
  429. IDL Master Timing
  430. IDL Slave Mode Timing, PLIC Ports 0–3
  431. IDL Slave Timing
  432. GCI Slave Mode Timing
  433. GCI Master Mode Timing
  434. General-Purpose I/O Port Timing
  435. USB Interface Timing
  436. IEEE 1149.1 (JTAG) Timing
  437. QSPI Timing
  438. PWM Timing
  439. A.1 List of Memory Map Tables
  440. A-2 CPU Space Registers Memory Map
  441. A-5 Chip Select Register Memory Map
  442. A-7 QSPI Module Memory Map
  443. A-10 UART0 Module Memory Map
  444. A-11 UART1 Module Memory Map
  445. A-12 SDRAM Controller Memory Map
  446. A-14 PLIC Module Memory Map
  447. A-15 Ethernet Module Memory Map
  448. A-16 USB Module Memory Map
  449. Physical Layer Interface Controller (PLIC
  450. Queued Serial Peripheral Interface (QSPI) Module
  451. Electrical Characteristics
NXP Semiconductors MCF5272 ColdFire User Manual Manual pdf 474 page image
Bus OperationMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 320-26 Freescale Semiconductor
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