MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor Index-1IndexAAccess control register, 4-14ACR0 and ACR1, 4-14Activate low-power register, 6-10Address bus, 20-2Address variant, 5-4Addressingmode summary, 2-12Addressing mode summary, 2-12Arbitration, bus, 20-21Architecture overview, 1-4Async inputs signal timing, 23-19Audience, 1-xlBBaud ratecalculating, 16-20selection, 14-6Branch instruction executiontiming, 2-25Buffer descriptorsEthernet, 11-34USB controller, 11-34Buffering and impedance matching, B-1Busarbitration, 20-21burst data transfers, 20-17configurations overview, 1-7data transfer mechanism, 20-4errors, 20-19exceptions, 20-3external interface, 1-5external interface types, 20-7interface for FLASH/SRAM, 20-8interrupt acknowledge cycles, 20-19master reset, 20-22misaligned operands, 20-18normal reset, 20-23read/write (R/W), 20-2reset operation, 20-21sizing, 20-4soft reset operation, 20-25software watchdog timer reset operation, 20-24transfer acknowledge (TA), 20-2transfer error acknowledge (TEA), 20-3Byte strobes, 20-8CCacheconfiguration register, 2-9registers, access control, 2-9Cache control register, 4-12Cachescoherency and validation, 4-8miss fetch algorithm/line fills, 4-10CAM interface, 11-6CCR, 2-6Chip selectbase registers, 8-3CS0 special case, 8-2option registers, 8-5overview, features, usage, 8-1registers, 8-2Chip selectsgeneral overview, 1-5Clock generator, USB, 12-4ColdFiredocumentation, 1-xliiiColdFire coreaddressing mode summary, 2-12condition code register (CCR), 2-6exception processing overview, 2-25features and enhancements, 2-1instruction set summary, 2-13integer data formats, 2-9programming model, 2-4status register, 2-8supervisor programming model, 2-7user programming mode, 2-4Condition code register, 2-6Conventionsnotational, 1-xlivterminology, 1-xlviiCoreversion 2overview, 1-4DDatabus, 20-2Debugattribute trigger register, 5-7BDM command set summary, 5-19
