NXP Semiconductors MCF5272 ColdFire User Manual Manual pdf 423 page image
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NXP Semiconductors MCF5272 ColdFire User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. MCF5272 ColdFire ® Integrated Microprocessor User's Manual,
  36. Overview
  37. general information
  38. acronyms and abbreviations
  39. MCF5272 Key Features
  40. MCF5272 Block Diagram
  41. MCF5272 Architecture
  42. System Integration Module (SIM)
  43. Power Management
  44. Timer Module
  45. Pulse-Width Modulation (PWM) Unit
  46. Features and Enhancements
  47. ColdFire Pipeline
  48. ColdFire Multiply-Accumulate Functionality Diagram
  49. Hardware Divide Unit
  50. ColdFire Programming Model
  51. Condition Code Register (CCR)
  52. MAC Programming Model
  53. Status Register (SR)
  54. Cache Control Register (CACR)
  55. Organization of Integer Data Formats in Data Registers
  56. Memory Operand Addressing
  57. Addressing Mode Summary
  58. Instruction Set Summary
  59. Supervisor-Mode Instruction Set Summary
  60. Instruction Timing
  61. MOVE Instruction Execution Times
  62. Move Long Execution Times
  63. Execution Timings—One-Operand Instructions
  64. Miscellaneous Instruction Execution Times
  65. Branch Instruction Execution Times
  66. Exception Vector Assignments
  67. Exception Stack Frame Form
  68. Processor Exceptions
  69. ColdFire MAC Multiplication and Accumulation
  70. General Operation
  71. MAC Instruction Set Summary
  72. Local Memory
  73. Local Memory Registers
  74. SRAM Base Address Register (RAMBAR)
  75. SRAM Initialization
  76. ROM Base Address Register (ROMBAR)
  77. Programming ROMBAR for Power Management
  78. Instruction Cache Overview
  79. Instruction Cache Block Diagram
  80. Caching Modes
  81. Reset
  82. Instruction Cache Operation as Defined by CACR[CENB,CEIB]
  83. CACR Field Descriptions
  84. Access Control Register Format (ACRn)
  85. Processor/Debug Module Interface
  86. PSTCLK Timing
  87. Real-Time Trace Support
  88. Begin Execution of Taken Branch (PST = 0x5)
  89. Example JMP Instruction Output on PST/DDATA
  90. Debug Programming Model
  91. Address Attribute Trigger Register (AATR)
  92. Address Breakpoint Registers (ABLR, ABHR)
  93. Configuration/Status Register (CSR)
  94. Data Breakpoint/Mask Registers (DBR and DBMR)
  95. Program Counter Breakpoint Register (PBR)
  96. Trigger Definition Register (TDR)
  97. Background Debug Mode (BDM)
  98. CPU Halt
  99. BDM Serial Interface Timing
  100. Receive BDM Packet
  101. BDM Command Set
  102. BDM Command Format
  103. Command Sequence Diagram
  104. Command Set Descriptions
  105. WAREG / WDREG Command Format
  106. Read Memory Location ( READ )
  107. WRITE Command Format
  108. WRITE Command Sequence
  109. NOP Command Format
  110. Definition of DRc Encoding—Read
  111. WDMREG BDM Command Format
  112. Theory of Operation
  113. Emulator Mode
  114. Processor Status, DDATA Definition
  115. PST/DDATA Specification for User-Mode Instructions
  116. Supervisor Instruction Set
  117. Recommended BDM Connector
  118. SIM Block Diagram
  119. Programming Model
  120. Module Base Address Register (MBAR)
  121. System Configuration Register (SCR)
  122. System Protection Register (SPR)
  123. Power Management Register (PMR)
  124. USB and USART Power Down Modes
  125. Activate Low-Power Register (ALPR)
  126. Device Identification Register (DIR)
  127. Watchdog Reset Reference Register (WRRR)
  128. Watchdog Counter Register (WCR)
  129. Interrupt Controller Block Diagram
  130. ColdFire Core
  131. Interrupt Control Register 1 (ICR1)
  132. Interrupt Control Register 2 (ICR2)
  133. Interrupt Source Register (ISR)
  134. Programmable Interrupt Transition Register (PITR)
  135. Programmable Interrupt Wakeup Register (PIWR)
  136. Programmable Interrupt Vector Register (PIVR)
  137. MCF5272 Interrupt Vector Table
  138. Boot CS0 Operation
  139. Chip Select Base Registers (CSBRn)
  140. Output Read/Write Strobe Levels versus Chip Select EBI Code
  141. Chip Select Option Registers (CSORn)
  142. SDRAM Controller Signals
  143. Pin TSOP SDRAM Pin Definition
  144. Interface to SDRAM Devices
  145. Internal Address Multiplexing (16-Bit Data Bus)
  146. SDRAM Configuration Register (SDCR)
  147. SDCR Field Descriptions
  148. SDRAM Timing Register (SDTR)
  149. Auto Initialization
  150. Performance
  151. SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port
  152. Example Setup Time Violation on SDRAM Data Input during Write
  153. Timing Refinement with Inverted SDCLK
  154. Timing Refinement with Effective CAS Latency
  155. SDRAM Read Accesses
  156. SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1
  157. SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1
  158. SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1
  159. SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1
  160. SDRAM Refresh Cycle
  161. Enter SDRAM Self-Refresh Mode
  162. Exit SDRAM Self-Refresh Mode
  163. DMA Data Transfer Types
  164. DMA Mode Register (DMR)
  165. DMA Interrupt Register (DIR)
  166. DMA Source Address Register (DSAR)
  167. DMA Destination Address Register (DDAR)
  168. Ethernet Block Diagram
  169. Transceiver Connection
  170. Ethernet Frame Format
  171. FEC Frame Reception
  172. CAM Interface
  173. Ethernet Address Recognition Flowchart
  174. Hash Table Algorithm
  175. Ethernet Error-Handling Procedure
  176. Ethernet Control Register (ECR)
  177. Interrupt Event Register (EIR)
  178. Interrupt Mask Register (EIMR)
  179. Interrupt Vector Status Register (IVSR)
  180. Receive Descriptor Active Register (RDAR)
  181. Transmit Descriptor Active Register (TDAR)
  182. MII Management Frame Register (MMFR)
  183. MII Speed Control Register (MSCR)
  184. FIFO Receive Bound Register (FRBR)
  185. FIFO Receive Start Register (FRSR)
  186. Transmit FIFO Watermark (TFWR)
  187. FIFO Transmit Start Register (TFSR)
  188. Receive Control Register (RCR)
  189. Maximum Frame Length Register (MFLR)
  190. Transmit Control Register (TCR)
  191. RAM Perfect Match Address Low (MALR)
  192. RAM Perfect Match Address High (MAUR)
  193. Hash Table High (HTUR)
  194. Hash Table Low (HTLR)
  195. Pointer-to-Receive Descriptor Ring (ERDSR)
  196. Pointer-to-Transmit Descriptor Ring (ETDSR)
  197. Receive Buffer Size (EMRBR)
  198. Initialization Sequence
  199. FEC Initialization
  200. Receive Buffer Descriptor (RxBD)
  201. RxBD Field Descriptions
  202. Transmit Buffer Descriptor (TxBD)
  203. Differences between MCF5272 FEC and MPC860T FEC
  204. Introduction
  205. The USB "Tiered Star" Topology
  206. USB Module Block Diagram
  207. Clock Generator
  208. Endpoint Controllers
  209. Register Description and Programming Model
  210. USB Frame Number Register (FNR)
  211. USB Real-Time Frame Monitor Register (RFMR)
  212. USB Real-Time Frame Monitor Match Register (RFMMR)
  213. USB Alternate Settings Register (ASR)
  214. USB Device Request Data 1 Register (DRR1)
  215. USB Specification Number Register (SPECR)
  216. USB Endpoint 0 IN Configuration Register (IEP0CFG)
  217. USB Endpoint 0 OUT Configuration Register
  218. USB Endpoint 0 Control Register (EP0CTL)
  219. USB Endpoint 1-7 Control Register (EPnCTL)
  220. USB Endpoint 0 Interrupt Mask (EP0IMR and General/Endpoint 0 Interrupt Registers (EP0ISR)
  221. USB Endpoints 1–7 Interrupt Status Registers (EPnISR)
  222. USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR)
  223. USB Endpoint 0-7 Data Registers (EPnDR)
  224. USB Endpoint 0-7 Data Present Registers (EPnDPR)
  225. Example USB Configuration Descriptor Structure
  226. USB Module Access Times
  227. Software Architecture and Application Notes
  228. FIFO Configuration
  229. Control, Bulk, and Interrupt Endpoints
  230. IN Endpoints
  231. Endpoint Halt Feature
  232. Recommended USB Line Interface
  233. USB Protection Circuit
  234. PLIC System Diagram
  235. GCI/IDL Receive Data Flow
  236. GCI/IDL B-Channel Receive Data Register Demultiplexing
  237. GCI/IDL B Data Transmit Register Multiplexing
  238. B-Channel Unencoded and HDLC Encoded Data
  239. D-Channel HDLC Encoded and Unencoded Data
  240. D-Channel Contention
  241. GCI/IDL Loopback Mode
  242. Periodic Frame Interrupt
  243. Interrupt Control
  244. PLIC Internal Timing Signal Routing
  245. Super Frame Sync Generation
  246. B1 Receive Data Registers P0B1RR–P3B1RR
  247. B2 Receive Data Registers P0B2RR – P3B2RR
  248. B1 Transmit Data Registers P0B1TR–P3B1TR
  249. D Transmit Data Registers P0DTR–P3DTR
  250. P0CR–P3CR Field Descriptions
  251. Loopback Control Register (PLCR)
  252. P0ICR–P3ICR Field Descriptions
  253. Periodic Status Registers (P0PSR–P3PSR)
  254. Aperiodic Status Register (PASR)
  255. GCI Monitor Channel Receive Registers (P0GMR–P3GMR)
  256. GCI Monitor Channel Transmit Registers (P0GMT–P3GMT)
  257. GCI Monitor Channel Transmit Abort Register (PGMTA)
  258. GCI Monitor Channel Transmit Status Register (PGMTS)
  259. GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
  260. GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
  261. GCI C/I Channel Transmit Status Register (PGCITSR)
  262. D-Channel Status Register (PDCSR)
  263. D-Channel Request Registers (PDRQR)
  264. Sync Delay Registers (P0SDR–P3SDR)
  265. Clock Select Register (PCSR)
  266. Application Examples
  267. Port 1 Configuration Register (P1CR)
  268. Port 1 Interrupt Configuration Register (P1ICR)
  269. ISDN SOHO PABX Example
  270. Standard IDL2 10-Bit Mode
  271. Standard IDL2 8-Bit Mode
  272. QSPI Block Diagram
  273. Interface and Pins
  274. QSPI RAM
  275. QSPI RAM Model
  276. Transmit RAM
  277. Transfer Delays
  278. Transfer Length
  279. QSPI Mode Register (QMR)
  280. QSPI Clocking and Data Transfer Example
  281. SPI Modes Timing
  282. QSPI Wrap Register (QWR)
  283. QSPI Interrupt Register (QIR)
  284. QSPI Address Register
  285. Command RAM Registers (QCR0–QCR15)
  286. Programming Example
  287. Timer Block Diagram
  288. Timer Mode Registers (TMR0–TMR3)
  289. Timer Reference Registers (TRR0–TRR3)
  290. Timer Event Registers (TER0–TER3)
  291. System Integration Module (SIM
  292. Serial Module Overview
  293. UART Module Programming Model
  294. UART Mode Registers 1 (UMR1n)
  295. UMR1n Field Descriptions
  296. UART Mode Register 2 (UMR2n)
  297. UART Status Registers (USRn)
  298. UART Clock-Select Registers (UCSRn)
  299. UART Command Registers (UCRn)
  300. UART Receiver Buffer (URBn)
  301. UART Transmitter Buffers (UTBn)
  302. UART Auxiliary Control Registers (UACRn)
  303. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
  304. UART Divider Upper Registers (UDUn)
  305. UART Transmitter FIFO Registers (UTFn)
  306. UART Receiver FIFO Registers (URFn)
  307. UART Fractional Precision Divider Control Registers (UFPDn)
  308. Interrupt Controller
  309. UART/RS-232 Interface
  310. Clocking Source Diagram
  311. External Clock
  312. Transmitter and Receiver Functional Diagram
  313. Transmitter Timing
  314. Receiver Timing
  315. Transmitter FIFO
  316. Looping Modes
  317. Automatic Echo
  318. Remote Loop-Back
  319. Multidrop Mode Timing Diagram
  320. UART Mode Programming Flowchart (Sheet 1 of 5)
  321. Port Control Registers
  322. Port A Control Register (PACNT)
  323. Port B Control Register (PBCNT)
  324. PBCNT Field Descriptions
  325. Port B Control Register Function Bits
  326. Port D Control Register (PDCNT)
  327. Port D Control Register Function Bits
  328. Port A Data Direction Register (PADDR)
  329. Port C Data Direction Register (PCDDR)
  330. PWM Block Diagram (3 Identical Modules)
  331. PWM Operation
  332. PWM Control Registers (PWCRn)
  333. PWM Width Register (PWWDn)
  334. MCF5272 Block Diagram with Signal Interfaces
  335. Signal List
  336. Signal Name and Description by Pin Number
  337. SDRAM Controller
  338. Bus Control Signals
  339. Read/Write (R/W)
  340. Transfer Acknowledge (TA/PB5)
  341. SDRAM Bank Selects (SDBA[1:0])
  342. General-Purpose I/O (GPIO) Ports
  343. Receive Serial Data Input (URT0_RxD/PB1)
  344. USB Transmit Data Negative (USB_TN/PA3)
  345. Ethernet Module
  346. Transmit Data (E_TxD0)
  347. Receive Error (E_RxER/PB14)
  348. QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL)
  349. Physical Layer Interface Controller TDM Ports and UART 1
  350. UART1 CTS (URT1_CTS/QSPI_CS2)
  351. GCI/IDL Data Out (DOUT1)
  352. GCI/IDL TDM Ports 2 and 3
  353. INT4 and Port 3 GCI/IDL Data In (INT4/DIN3)
  354. Test and Debug Data Out (TDO/DSO)
  355. Debug Data (DDATA[3:0])
  356. Power Supply Pins
  357. Features
  358. Address Bus (A[22:0])
  359. Transfer Error Acknowledge (TEA)
  360. Data Transfer Mechanism
  361. Internal Operand Representation
  362. Byte Strobe Operation for 32-Bit Data Bus
  363. External Bus Interface Types
  364. Longword Read; EBI = 00; 32-Bit Port; Internal Termination
  365. Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination
  366. Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination
  367. Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination
  368. Longword Read; EBI=11; 32-Bit Port; Internal Termination
  369. Word Write; EBI=11; 16/32-Bit Port; Internal Termination
  370. Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination
  371. Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination
  372. Burst Data Transfers
  373. Example of a Misaligned Longword Transfer
  374. Interrupt Cycles
  375. Longword Write Access To 32-Bit Port Terminated with TEA Timing
  376. Bus Arbitration
  377. Master Reset Timing
  378. Normal Reset Timing
  379. Software Watchdog Timer Reset Timing
  380. Soft Reset Timing
  381. Test Access Port Block Diagram
  382. TAP Controller State Machine
  383. Output Cell (O.Cell) (BC–1)
  384. Input Cell (I.Cell). Observe only (BC–4)
  385. Bidirectional Cell (IO.Cell) (BC–6)
  386. Instruction Register
  387. Bypass Register
  388. MCF5272 Pinout (196 MAPBGA)
  389. MAPBGA Package Dimensions (Case No. 1128A-01)
  390. Maximum Ratings
  391. Operating Temperature
  392. DC Electrical Specifications
  393. Clock Input Timing Diagram
  394. Processor Bus Input Timing Specifications
  395. General Input Timing Requirements
  396. Processor Bus Output Timing Specifications
  397. Read/Write SRAM Bus Timing
  398. SRAM Bus Cycle Terminated by TA
  399. SRAM Bus Cycle Terminated by TEA
  400. Reset and Mode Select/HIZ Configuration Timing
  401. Real-Time Trace AC Timing
  402. SDRAM Interface Timing Specifications
  403. SDRAM Signal Timing
  404. SDRAM Self-Refresh Cycle Timing
  405. MII Receive Signal Timing Diagram
  406. MII Transmit Signal Timing Diagram
  407. MII Async Inputs Timing Diagram
  408. MII Serial Management Channel Timing Diagram
  409. Timer Timing
  410. UART Timing
  411. IDL Master Timing
  412. IDL Slave Mode Timing, PLIC Ports 0–3
  413. IDL Slave Timing
  414. GCI Slave Mode Timing
  415. GCI Master Mode Timing
  416. General-Purpose I/O Port Timing
  417. USB Interface Timing
  418. IEEE 1149.1 (JTAG) Timing
  419. QSPI Timing
  420. PWM Timing
  421. A.1 List of Memory Map Tables
  422. A-2 CPU Space Registers Memory Map
  423. A-5 Chip Select Register Memory Map
  424. A-7 QSPI Module Memory Map
  425. A-10 UART0 Module Memory Map
  426. A-11 UART1 Module Memory Map
  427. A-12 SDRAM Controller Memory Map
  428. A-14 PLIC Module Memory Map
  429. A-15 Ethernet Module Memory Map
  430. A-16 USB Module Memory Map
  431. Physical Layer Interface Controller (PLIC
  432. Queued Serial Peripheral Interface (QSPI) Module
  433. Electrical Characteristics
/ 545
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