Flash MemoryMPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 591It is recommended to leave UT0.AIS at 1 and use the linear address sequence that takes lesstime.During the execution of the Margin mode operation it is forbidden to modify the content of Block Select(LMS, HBS) and Lock (LML, SLL, HBL) registers, otherwise the MISR value can vary in anunpredictable way.The read accesses will be done with the addition of a proper number of Wait States to guarantee thecorrectness of the result.While UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Array Integrity Checkabort.UT0.AID must be checked to know when the aborting command has completed.Example 17-6. Margin Read Check versus 1sUT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */UT0 = 0x80000004; /* Set AIS in UT0: Select Operation */UT0 = 0x80000024; /* Set MRE in UT0: Select Operation */UT0 = 0x80000034; /* Set MRV in UT0: Select Margin versus 1’s */UT0 = 0x80000036; /* Set AIE in UT0: Operation Start */do /* Loop to wait for AID=1 */{ tmp = UT0; /* Read UT0 */} while ( !(tmp & 0x00000001) );data0 = UMISR0; /* Read UMISR0 content*/data1 = UMISR1; /* Read UMISR1 content*/data2 = UMISR2; /* Read UMISR2 content*/data3 = UMISR3; /* Read UMISR3 content*/data4 = UMISR4; /* Read UMISR4 content*/UT0 = 0x80000034; /* Reset AIE in UT0: Operation End */UT0 = 0x00000000; /* Reset UTE, MRE, MRV, AIS in UT0: Deselect Op. */ECC logic checkECC logic can be checked by forcing the input of ECC logic: The 64 bits of data and the 8 bits of ECCsyndrome can be individually forced and they will drive simultaneously at the same value the ECC logicof the whole page (2 Double Words).The results of the ECC Logic Check can be verified by reading the MISR value.The ECC Logic Check operation consists of the following sequence of events:1. Set UTE in UT0 by writing the related password in UT0.2. Write in UT1.DAI31-0 and UT2.DAI63-32 the Double Word Input value.3. Write in UT0.DSI7-0 the Syndrome Input value.4. Select the ECC Logic Check: write a logic 1 to the UT0.EIE bit.5. Write a logic 1 to the UT0.AIE bit to start the ECC Logic Check.6. Wait until the UT0.AID bit goes high.7. Compare UMISR0-4 content with the expected result.8. Write a logic 0 to the UT0.AIE bit.
