Quad Serial Peripheral Interface (QuadSPI)MPC5606S Microcontroller Reference Manual, Rev. 71068 Freescale SemiconductorNote also that the serial flash device clock SCK is inverted w.r.t. theQuadSPI internal reference clock.Figure 30-37. Serial Flash Sampling Clock TimingThe rising edge of the internal reference clock is taken as timing reference for the data output of the serialflash. After a time of tDel,total the data arrive at the internal sampling stage of the QuadSPI module.According to Figure 30-36 the following parts of the delay chain contribute to tDel,total:1. Output delay of the serial flash clock output of the device containing the QuadSPI module2. Wire delay of application/PCB from the device containing the QuadSPI module to the externalserial flash device3. Clock to data out delay of the external serial flash device, including input and output delays4. Wire delay of application/PCB from the external serial flash device to the device containing theQuadSPI module5. Input delay belonging to the data in inputThe possible points in time for the sampling of the incoming data are denoted as N/1, I/1, N/2 and I/2above. The sampling point relevant for the internal sampling is configured in the QSPI_SMPR register,refer to Section 30.4.3.13, Sampling Register (QSPI_SMPR), for details. Note that the falling edges of thereference clock are not actually used, instead the inverted clock is used for sampling at these positions.Table 30-54 below gives an overview of the available configurations for the commands running at regular(full) speed:internal ref clockserial flash datainternal reference for serial flash data samplingtDel,totalN/1 N/2I/1 I/2Possible Sampling PointsSCK—serial flash clock
