Deserial Serial Peripheral Interface (DSPI)MPC5606S Microcontroller Reference Manual, Rev. 7296 Freescale Semiconductor10–11PASC[0:1]After SCK Delay Prescaler. The PASC field selects the prescaler value for the delay between the lastedge of SCK and the negation of PCS. This field is used only in Master mode. The table below liststhe prescaler values. See the ASC[0:3] field description for details on how to compute the After SCKDelay.12–13PDT[0:1]Delay after Transfer Prescaler. The PDT field selects the prescaler value for the delay between thenegation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of thenext frame. The PDT field is used only in Master mode. The table below lists the prescaler values.See the DT[0:3] field description for details on how to compute the Delay after Transfer.14–15PBR[0:1]Baud Rate Prescale. The PBR field selects the prescaler value for the baud rate. This field is usedonly in Master mode. The baud rate is the frequency of the Serial Communications Clock (SCK). Thesystem clock is divided by the prescaler value before the baud rate selection takes place. The BaudRate Prescaler values are listed in the table below. See the BR[0:3] field description for details onhow to compute the baud rate.16–19CSSCK[0:3]PCS to SCK Delay Scaler. The CSSCK field selects the scaler value for the PCS to SCK delay. Thisfield is used only in Master mode. The PCS to SCK Delay is the delay between the assertion of PCSand the first edge of the SCK. Table 11-8 list the scaler values.The PCS to SCK Delay is a multipleof the system clock period and it is computed according to the following equation:Eqn. 11-1Table 11-5. DSPIx_CTARn field descriptions (continued)Field DescriptionsPASC After SCK delay prescaler value00 101 310 511 7PDT Delay after transfer prescaler value00 101 310 511 7PBR Baud rate prescaler value00 201 310 511 7t CSC1f SYS----------- PCSSCK CSSCK=
