FlexCANMPC5606S Microcontroller Reference Manual, Rev. 7680 Freescale SemiconductorBase + 0x00000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15RMDISFRZ FENHALTNOT_RDY0SOFT_RSTFRZ_ACKSUPV 0 WRN_ENLPM_ACK0 0SRX_DISBCCWReset — 11 Reset value of this bit is different on various platforms. Consult the specific MCU documentation to determine itsvalue.1 0 1 1 0 0 — 22 Different on various platforms, but it is always the opposite of the MDIS reset value.1 0 0 — 33 Different on various platforms, but it is always the same as the MDIS reset value.0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0LPRIO_ENAEN 0 0 IDAM 0 0 MAXMBWReset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1Figure 18-5. Module Configuration Register (MCR)Table 18-8. MCR field descriptionsField DescriptionMDIS Module DisableThis bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down theclocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the onlybit in MCR not affected by soft reset. See Section 18.4.9.2, Module Disable mode, for moreinformation.0 Enable the FlexCAN module1 Disable the FlexCAN moduleFRZ Freeze EnableThe FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR Register is set or whenthe MCU is stopped by a debugger. When FRZ is asserted, FlexCAN is enabled to enter Freezemode. Negation of this bit field causes FlexCAN to exit from Freeze mode.0 Not enabled to enter Freeze mode1 Enabled to enter Freeze modeFEN FIFO EnableThis bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannotbe used for normal reception and transmission because the corresponding memory region(0x80–0xFF) is used by the FIFO engine. See Section 18.3.3, Rx FIFO Structure, andSection 18.4.7, Rx FIFO, for more information.0 FIFO not enabled1 FIFO enabled
